16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion | NXP Semiconductors

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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion

GTL1655DGG
No Longer Manufactured
  • This page contains information on a product that is no longer manufactured (discontinued). Specifications and information herein are available for historical reference only.

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The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 Ω) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.

The device is configured as two 8-bit transceivers that share a common clock and a leader output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes.

The GTL1655 can be used at GTL (VTT= 1.2 V, VREF= 0.8 V) or GTL+ (VTT= 1.5 V, VREF= 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with VREF providing the reference voltage input.

The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins.

To optimize signal integrity, the GTL1655 features an adjustable edge rate control (VERC). By adjusting VERC between GND and VCC, a designer can adjust the Port B edge rate to suit an application?s load conditions.

The GTL1655 permits true live insertion capability by incorporating:

  • BIAS VCC , to pre-charge outputs and avoid disturbing active data during card insertion.
  • Ioff to disable current flow through powered-off I/Os.
  • Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.
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CAD Model

Application

Function

Operating Temperature (°C)

Voltage Translation Range

TTL Drive

GTL Drive

Number of bits

GTL1655DGG
Data Sheet

Processor Interface/Backplane

Universal Bus Transceiver

-40~85

1.14 to 1.65 ~ 3.0 to 5.5

24

100

16

N true 0 PSPGTL1655DGGen 4 Application Note Application Note t789 1 Brochure Brochure t518 1 Data Sheet Data Sheet t520 1 Package Information Package Information t790 1 en_US en_US en Data Sheet Data Sheet 1 1 1.0 English 1442050930212718392619 PSP 127.0 KB None None documents None 1442050930212718392619 /docs/en/data-sheet/GTL1655.pdf 127000 /docs/en/data-sheet/GTL1655.pdf GTL1655 documents N 2015-09-12 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion /docs/en/data-sheet/GTL1655.pdf /docs/en/data-sheet/GTL1655.pdf Data Sheet N 980000996212993340 2022-12-07 pdf en May 11, 2004 980000996212993340 Data Sheet Y N 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Application Note Application Note 1 2 1.0 English 1442087689485731980491 PSP 4.3 MB None None documents None 1442087689485731980491 /docs/en/application-note/AN10216.pdf 4320295 /docs/en/application-note/AN10216.pdf AN10216 documents N N 2016-07-05 AN10216 /docs/en/application-note/AN10216.pdf /docs/en/application-note/AN10216.pdf Application Note N 645036621402383989 2024-10-21 pdf N en Mar 27, 2003 645036621402383989 Application Note Y N AN10216 Brochure Brochure 1 3 2.0 English 1442124514333705271421 PSP 2.4 MB None None documents None 1442124514333705271421 /docs/en/nxp/brochures/75017511.pdf 2434654 /docs/en/nxp/brochures/75017511.pdf 75017511 documents N N 2016-10-08 Voltage Translation: How to manage mixed-voltage designs with NXP level translators /docs/en/nxp/brochures/75017511.pdf /docs/en/nxp/brochures/75017511.pdf Brochure N 712453003803778552 2024-03-13 pdf N en Feb 15, 2023 712453003803778552 Brochure Y N Voltage Translation: How to manage mixed-voltage designs with NXP level translators Package Information Package Information 1 4 1.0 English 1455079132556717005302 PSP 553.0 KB None None documents None 1455079132556717005302 /docs/en/package-information/SOT646-1.pdf 553000 /docs/en/package-information/SOT646-1.pdf SOT646-1 documents N 2016-02-09 plastic thin shrink small outline package; 64 leads; body width 6.1 mm /docs/en/package-information/SOT646-1.pdf /docs/en/package-information/SOT646-1.pdf Package Information N 302435339416912908 2022-12-07 pdf en Feb 8, 2016 302435339416912908 Package Information Y N plastic thin shrink small outline package; 64 leads; body width 6.1 mm false 0 GTL1655DGG downloads en true 1 Y PSP Application Note 1 /docs/en/application-note/AN10216.pdf 2016-07-05 1442087689485731980491 PSP 2 Mar 27, 2003 Application Note None /docs/en/application-note/AN10216.pdf English documents 4320295 None 645036621402383989 2024-10-21 N /docs/en/application-note/AN10216.pdf AN10216 /docs/en/application-note/AN10216.pdf documents 645036621402383989 Application Note N en None Y pdf 1.0 N N AN10216 4.3 MB AN10216 N 1442087689485731980491 Brochure 1 /docs/en/nxp/brochures/75017511.pdf 2016-10-08 1442124514333705271421 PSP 3 Feb 15, 2023 Brochure None /docs/en/nxp/brochures/75017511.pdf English documents 2434654 None 712453003803778552 2024-03-13 N /docs/en/nxp/brochures/75017511.pdf Voltage Translation: How to manage mixed-voltage designs with NXP level translators /docs/en/nxp/brochures/75017511.pdf documents 712453003803778552 Brochure N en None Y pdf 2.0 N N Voltage Translation: How to manage mixed-voltage designs with NXP level translators 2.4 MB 75017511 N 1442124514333705271421 Data Sheet 1 /docs/en/data-sheet/GTL1655.pdf 2015-09-12 1442050930212718392619 PSP 1 May 11, 2004 Data Sheet None /docs/en/data-sheet/GTL1655.pdf English documents 127000 None 980000996212993340 2022-12-07 /docs/en/data-sheet/GTL1655.pdf 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion /docs/en/data-sheet/GTL1655.pdf documents 980000996212993340 Data Sheet N en None Y pdf 1.0 N 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 127.0 KB GTL1655 N 1442050930212718392619 Package Information 1 /docs/en/package-information/SOT646-1.pdf 2016-02-09 1455079132556717005302 PSP 4 Feb 8, 2016 Package Information None /docs/en/package-information/SOT646-1.pdf English documents 553000 None 302435339416912908 2022-12-07 /docs/en/package-information/SOT646-1.pdf plastic thin shrink small outline package; 64 leads; body width 6.1 mm /docs/en/package-information/SOT646-1.pdf documents 302435339416912908 Package Information N en None Y pdf 1.0 N plastic thin shrink small outline package; 64 leads; body width 6.1 mm 553.0 KB SOT646-1 N 1455079132556717005302 true Y Products

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