202104033I : PCF8551 Datasheet 9 Clock Pulses after Power-On Requirement
7.3 Starting and Resetting the PCF8551 Added "See also application information" comment. 7.3.2 Power-On Reset (POR) Added "The bus interface is initialized" comment. 15.1 Power-on Reset The built-in POR block acts on the rising edge of the VDD supply voltage. Depending on the VDD rising edge in the application the POR may not work properly. Therefore to ensure proper device operation it is required to send nine clock pulses immediately after power-on (see also UM10204).
| PCN Type | Change Category | Issue Date | Effective Date |
|---|---|---|---|
| Customer Information Notification | Errata | 23-Apr-2021 | 30-Apr-2021 |
Reason of Change
The intend of these updates is to ensure that the customers send nine clock pulses immediately after power-on (see also UM10204) for the proper device operation; if the POR does not work properly.
Anticipated Impact
Data sheet revision: A new datasheet will be issued
Affected Parts
| Part Number / 12NC | Last Time Buy Date | Last Time Delivery Date | Replacement Part |
|---|---|---|---|
|
PCF8551ATT/AJ (935304761118) |
- | - | - |
|
PCF8551ATT/AY (935304761518) |
- | - | - |
|
PCF8551BTT/AJ (935305822118) |
- | - | - |
|
PCF8551BTT/AY (935305822518) |
- | - | - |