202004027I : MPC5645S Errata Update to Rev 20 Apr 2020
NXP Semiconductors is announcing an update of errata for the MPC5645S for mask sets 0N29D and 1N29D.The errata for both mask sets will be updated from revision 20/Feb/2015 to revision 20/Apr/2020.The revision history included in the updated documents provide detailed descriptions of the changes.Errata changes for mask sets 0N29D and 1N29D:1) Erratum ERR011214: MDDRC Do not perform unaligned address transfers to MDDRC from different bus masters (e.g: PowerPC core) was added.2) Erratum ERR050459: SXOSC Clock output may contain extra clock pulses in Normal mode was added.Users are advised to go through the new erratum and implement the respective work around if applicable to avoid application issues.The MPC5645S errata revision 20Apr2020 are attached to this notification and can be found at:https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/mpc55xx-5xxx-mcus/ultra-reliable-mpc56xx-mcus/ultra-reliable-mpc56xs-mcu-for-automotive-industrial-instrument-clusters:MPC564xS?tab=Documentation_TabCorresponding ZVEI Delta Qualification Matrix ID: SEM-DS-02.
| PCN Type | Change Category | Issue Date | Effective Date |
|---|---|---|---|
| Customer Information Notification | Errata | 09-May-2020 | 10-May-2020 |
Reason of Change
The errata have been updated to provide additional technical clarification.
Identification of Affected Products
Product identification does not change
Anticipated Impact
No impact on form fit function reliability or quality.
Affected Parts
| Part Number / 12NC | Last Time Buy Date | Last Time Delivery Date | Replacement Part |
|---|---|---|---|
|
SPC5645SF1VLT (935314839557) |
- | - | - |
|
SPC5645SF1VLTR (935314839528) |
- | - | - |
|
SPC5645SF1VLU (935313103557) |
- | - | - |
|
SPC5645SF1VLUR (935313103528) |
- | - | - |
|
SPC5645SF1VVU (935320123557) |
- | - | - |
|
SPC5645SF1VVUR (935320123518) |
- | - | - |