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Design Rule Verification Report

Date : 15.08.2016
Time : 10:50:18
Elapsed Time : 00:00:01
Filename : V:\01_projects\PCB-Service\PCB Projects\2016\LID2262 Customer PHY Board_V6\Protel_DXP_Daten\PCB\LID2262.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Width Constraint (Min=8.661mil) (Max=8.661mil) (Preferred=8.661mil) (InNetClass('Differential')) 0
Silk To Solder Mask (Clearance=0.5mil) (IsPad),(All) 0
Clearance Constraint (Gap=8.661mil) (InPoly),(All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (IsVia) 0
Minimum Annular Ring (Minimum=5.905mil) ((IsVia)) 0
Minimum Annular Ring (Minimum=-100mil) ((IsPad AND not PadIsPlated)) 0
Width Constraint (Min=6.693mil) (Max=6.693mil) (Preferred=6.693mil) (Disabled)(All) 0
Clearance Constraint (Gap=5.905mil) (Disabled)(InComponentClass('FinePitch')),(All) 0
Clearance Constraint (Gap=12mil) (Disabled)(All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Power Plane Connect Rule(Relief Connect )(Expansion=7.874mil) (Conductor Width=7.874mil) (Air Gap=9.842mil) (Entries=4) (All) 0
Width Constraint (Min=5.905mil) (Max=78.74mil) (Preferred=7.874mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (Disabled)(All) 0
Hole Size Constraint (Min=15.748mil) (Max=196.85mil) (All) 0
Clearance Constraint (Gap=5.905mil) (All),(All) 0
Width Constraint (Min=4mil) (Max=100mil) (Preferred=8mil) (Disabled)(All) 0
Minimum Annular Ring (Minimum=7.874mil) (Disabled)((IsPad)) 0
Minimum Annular Ring (Minimum=5.905mil) (Disabled)((IsPad)) 0
Hole Size Constraint (Min=7.874mil) (Max=196.85mil) (All) 0
Hole Size Constraint (Min=11.811mil) (Max=196.85mil) (Disabled)(All) 0
Minimum Annular Ring (Minimum=7.874mil) (Disabled)((IsVia)) 0
Hole Size Constraint (Min=7.874mil) (Max=787.402mil) (Disabled)((IsPad AND not PadIsPlated)) 0
Total 0