ISSUE DATE: | 23-Oct-2009 |
NOTIFICATION: | 13903 |
TITLE: | 9S12XDP512 (L15Y TSMC FAB) ROOM TEST ELIMINATION |
EFFECTIVE DATE: | 06-Nov-2009 |
MPN |
---|
MC9S12XA512CAA |
MC9S12XA512CAG |
MC9S12XA512CAL |
MC9S12XA512VAA |
MC9S12XA512VAL |
MC9S12XDP512CAG |
MC9S12XDP512CAL |
MC9S12XDP512MAG |
MC9S12XDP512MAL |
MC9S12XDP512VAG |
MC9S12XDP512VAL |
MC9S12XDT512CAA |
MC9S12XDT512CAG |
MC9S12XDT512CAL |
MC9S12XDT512MAA |
MC9S12XDT512MAG |
MC9S12XDT512MAL |
MC9S12XDT512VAL |
S912XD128J1CAA |
S912XD128J1CAAR |
S912XD256J1CAG |
S912XD256J1MAA |
S912XD256J1VAG |
S912XD256J1VAGR |
S912XDG256J1VAG |
S912XDG256J1VAGR |
S912XDG512J1CAG |
S912XDG512J1CAGR |
S912XDP512J0CAL |
S912XDP512J0CALR |
S912XDP512J0MAG |
S912XDP512J0MAL |
S912XDP512J0VAL |
S912XDP512J0VALR |
S912XDP512J1CAA |
S912XDP512J1CAAR |
S912XDP512J1CAG |
S912XDP512J1CAGR |
S912XDP512J1CAL |
S912XDP512J1CALR |
S912XDP512J1MAG |
S912XDP512J1MAGR |
S912XDP512J1MAL |
S912XDP512J1MALR |
S912XDP512J1VAG |
S912XDP512J1VAGR |
S912XDP512J1VAL |
S912XDT256J0VAL |
S912XDT256J1MAL |
S912XDT256J1VAL |
S912XDT384J0CAG |
S912XDT384J0CAGR |
S912XDT384J1CAA |
S912XDT384J1CAAR |
S912XDT384J1CAG |
S912XDT384J1CAGR |
S912XDT384J1CAL |
S912XDT384J1CALR |
S912XDT384J1MAG |
S912XDT384J1MAL |
S912XDT384J1MALR |
S912XDT384J1VAG |
S912XDT384J1VAL |
S912XDT384J1VALR |
S912XDT512J0CAA |
S912XDT512J0MAA |
S912XDT512J1CAA |
S912XDT512J1CAAR |
S912XDT512J1CAG |
S912XDT512J1CAGR |
S912XDT512J1CAL |
S912XDT512J1MAA |
S912XDT512J1VAA |
S912XDT512J1VAG |
S912XDT512J1VAGR |
S912XDT512J1VAL |
SC104002VPV |
SC104002VPVR2 |
Freescale is announcing the ROOM test elimination for the Final Test production flow for the 9S12XDP512 (L15Y mask set) for all market applications. The ROOM test is covered by the remaining Final Test COLD and HOT temperature production test(s).
Improve capacity for optimized cycle time and delivery.
None.
To eliminate production tests, the acceptable number of failures using a minimum sample size of 100,000 units, is zero. The units are to be obtained from a minimum of 12 separate wafer lots, from the same fab, same mask set, each lot processed in a different time frame/day than others, over a nine week period of time, to make certain that all lots are non-consecutive.
This device is fully qualified. No further Reliability data is needed for this change.
The ROOM test elimination was successfully completed after testing 118k units, representing twelve different wafer lots, processed in the same wafer fabrication facility, same mask set, over a nine week period, with zero ROOM test failures.
There is no change to the orderable part number or marking.