If the S12X_CPU and the XGATE attempt to lock a semaphore at the same

time the S12X_CPU will obtain the semaphore, but the Carry-Flag will be

set for the XGATE (falsely indicating that the XGATE has locked the

semaphore). 

Execute two consecutive "SSEM" instructions to set a semaphore. Ignore

result of the first "SSEM" instruction. Carry-Flag will indicate

correctly whether XGATE has allocated the semaphore after the second

"SSEM" instruction is executed. 

Normal Operation:



Timer Free Running Counter, also called as Timer Counter resets to

0x0000 on a Channel 7 Output Compare event when Timer Counter Reset

Enable (TCRE) bit of TSCR2 registers is set to 1. This assumes that

TIOS7 bit of TIOS register is set to a 1 (Output Compare mode).



Issue: Erroneously this behaviour was found to occur even when 

TIOS7 bit of TIOS register was set to a "0" (Input Capture mode) 

Reseting Free Running Counter alias Timer Counter can be avoided by

setting Timer Counter Reset Enable (TCRE) bit of TSCR2 register to a "0".   

Problem:

Normal Operation: 

With TIOS = 1 (Output Compare mode) and TFFCA = 1 (Fast Flag Clearing

mechanism) a write to TCx register following an output compare event

clears the flag. 



Erroneous Operation: 

A read to TCx register following an Output Compare event clears Cxf flag

in TFLG1 register.  

Customer should avoid reading TCx register following an Ouput Compare event. 

Normal Operation: 

With TIOS = 0 (Input Capture (IC) mode) and TFFCA = 1 (Fast Flag

Clearing mechanism) a read to TCx register following an Input Capture

(IC) event clears CxF (flag) bit of TFLG1 register.



Erroneous Operation: 

A write to TCx register following an Input Capture (IC) event clears Cxf

(flag) bit  of TFLG1 register.  

Customer should avoid writing to TCx register following an Input Capture

(IC) event. 

Correct Operation:



Forced Output Compare (OC) operation on channel 7 requires TIOS7 bit be

set to a “1” for a successful Ouput Compare (OC) event.



Faulty Operation:



Forced Ouput Compare (OC) action was noticed on Channel 7 inspite of

TIOS7 being set to a “0”. 

None. 

Correct Operation:



When timer is enabled (TEN bit of TSCR1 register is set to 1) and Output

Compare functionality is selected (TIOSx bit of TIOS register is set) on

a match (TCNT = Tcx) an output compare event(dictated by OM/OL bits of

TCTL1/TCTL2 register) is generated. Please not that the Output Compare

is registered internally.



Faulty Operation:



Consider a case, when an normal Output Compare event (driving port to 1)

was performed. You intend to dis-connect output compare logic from pin

logic. Hence you configure (OM/OL bits to a “0”), but your TIOSx bit is

still set to a “1”. Also, you intend to use masking feature of output

compare so you set TIOS7=1 and you have OC7Mx bit set to a “1”. If the

next output compare match(TCNT = Tcx) happens to be normal output

compare event, the default state of internal register (0) was noticed on

the channel.



In reality the output port should not have toggled since OM/OL were set

to 0.

This is an erroneous behaviour. 

Make sure that OC7Mx bit is set to "0" if not using OC7M feature for

that channel. If using masking feature, please remember to set OC7Mx bit

to "0" as soon as you have a channel 7 Compare event. 

The effective address calculated by the CALL instruction using PC

relative addressing is one / two less than it should be. 

With the result that the CALL ends one / two byte(s) 

before the intended destination. 



Affected indexed addressing modes: 

   IDX 5-bit offset 

      1 less 

   IDX Accumulator offset 

      1 less 

   IDX1 

      2 less  

Take into account the extra constant offsets when using PC relative

addressing of CALL. 

Under the following condition, the CPU ignores a tag hit and executes

the tagged instruction when it should not: 



1. The CPU has finished an instruction and is going to execute a page2

instruction next, prebyte 0x18 already in the instruction register... 



2. ...at the same time an interrupt is pending, so the CPU does not

execute the page2 instruction, but starts to perform the Interrupt

sequence "VSPSSPSSP". 



3. The first instruction of the Interrupt Service Routine has been 

tagged and the corresponding taghit action is asserted, so the CPU 

should not execute the tagged instruction, but start a SWI/BDM 

sequence.

But this does not happen, the tag is ignored and the instruction is

executed. 

None. 

Writing to the read only register DBGMFR actually performs a write

access of DBGSCR3.



Thus DBGSCR3 is loaded with the data of the attempted write to DBGMFR.

DBGMFR cannot be written and is thus not affected. 

Do not write to the read only register DBGMFR. 

When using a comparator pair for a range comparison, the databus can

also be used for qualification by using the comparator A/C data and data

mask registers. This does not work correctly.



Scenario:

With CompA/CompB in outside range mode an access to a memory location

with an address above the high boundary of CompB always generates a

comparator match. The data qualification is not carried out.



If the accessed memory is located below the address defined in CompA,

the behavior is correct.



CompC/CompD behavior is the same.  

Using 2 comparator pairs configured for inside range mode an outside

range match with databus qualification can be generated.



MAP       

0x000000 |COMPA|

         |     | Inside Range A/B with DB qualification

ADDRESSX |COMPB| 

         |     |

ADDRESSY |COMPC|

         |     | Inside Range C/D with DB qualification

0x7FFFFF |COMPD| 

The comparator A and C TAG bits are used to tag range comparisons for

the AB and CD ranges respectively. The comparator B and D TAG bits

should have no effect in range modes. However the TAGB/TAGD bits do have

an effect.

If the A/C TAG bit is 0 but the paired B/D TAG bit is set a valid match

may be missed.  

Clear TAGB when configured for forced range mode comparisons using CompAB 

Clear TAGD when configured for forced range mode comparisons using CompCD    

This is a debug issue only.

 

If a CPU bus cycle is requested, but not acknowledged immediately, a

wrong trace buffer entry may happen.

 

Example scenario:

XGATE accesses PRR -> CPU is not immediately acknowledged.

 

Frequency of occurrence:

This issue will only manifest during BDM steal and simultaneous XGATE

PRR access during trace capture. 

None. 

Starting a conversion with a write to ATDxCTL5 or on an external trigger

event, and aborting immediately afterwards with a write to ATDxCTL0,

ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the conversion process. 

Only write to ATDxCTL4 to abort an ongoing conversion sequence.



Use the recommended start and abort procedures from the Block Guide.

Section : Initialization/Application Information 

Subsection: Setting up and starting an A/D conversion 

Subsection: Aborting an A/D conversion 

If the range of Flash addresses to be compressed is 32K or greater, the

data at one of the addresses will be effectively ignored. The address

affected is 32K from the upper address read in the data compress

algorithm, e.g., for an address range of 32K, the first data read in the

algorithm will not affect the final signature provided by the algorithm.

 

Limit range of addresses to be compressed to less than 32K addresses.

Execute multiple data compress commands to compress larger Flash address

ranges. 

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is

sampled leading to an early-SOF*.



The CRC is calculated from the resulting bit stream so that the

receiving nodes will still validate the message.



An early-SOF condition may only occur if the oscillators in the network

operate at a tolerance range which could lead to a cumulated phase error

after 11 bit times larger than phase segment 2. 



In case arbitration is lost during transmission of the corrupt

identifier, a non-corrupted ID will be sent with the next attempt if the

transmit request remains active.



*The CAN protocol condition referred to as 'early-SOF' in this erratum

is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,

and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B. 

Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided

when calculating the maximum oscillator tolerance of the overall CAN

system. The phase error after 11 bit times due to the oscillator

tolerance should be smaller than phase segment 2.



If an early-SOF cannot be avoided the following methods will provide

prevention:



- Assigning the same value to all upper eight ID bits in the network

- Allocating dedicated data length codes (DLC) to every identifier used 

  in the network and checking for correspondence after reception

- Assigning only IDs (x) which do not consist of a combination of other 

  assigned IDs (y,z) and using the acceptance filters to reject 

  erroneous messages, i.e. 

  - for standard frames: IDx[11:0]  != {IDy[11:3], IDz[2:0]}

  - for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]} 

Memory accesses in successive bus cycles must both be able to generate

forced triggers if both accesses match. 



If accesses occur in successive cycles whereby the second access is a

misaligned word access, then a comparator match is lost. This could

cause a forced breakpoint to be missed if the state sequencer is

dependent on both the successive matches to reach final state. 

Example... 

        LDX    #WORD_MISALIGNED

        STD    0,X               ; First access M0->State2

        LDD    WORD_MISALIGNED   ; Second access M0->Final State



If the STD last bus cycle is a write and the LDD first bus cycle is a

read then only one state sequencer transition occurs.



In range modes, this can occur when 2 different addresses within/outside

the specified range are accessed in successive bus cycles, otherwise it

can only happen if the same address is written and then read in

successive bus cycles. 

Insert a NOP instruction before misaligned word accesses if they can 

follow accesses to the predefined comparator range.





        LDX    #WORD_MISALIGNED-1

        STD    0,X               ; First access in range M0->State2

        NOP                      ; NOP insertion

        LDD    WORD_MISALIGNED   ; Second access in range M0->Final 

State

 

If configured for Pure PC mode tracing then an extra, unexpected trace

buffer entry may be encountered, by one of the 2 following scenarios.



1) At a tagged breakpoint to the CPU the trace buffer stores the opcode

address of the tagged instruction although it is not executed. 



2) When a BACKGROUND command forces BDM the address of the first opcode

following BDM is stored to the trace buffer befored entering BDM.



In both cases the extra trace buffer entry is of the first opcode

address following the breakpoint routine. Thus if tracing is not

terminated in the breakpoint routine, then the same entry appears twice

in the trace buffer.

If tracing is terminated in the breakpoint routine, the last trace

buffer entry is incorrect, since it points to the next instruction,

which has not yet been executed.

 

None. 

An interrupt request immediately following execution of a STOP 

instruction may cause the EEPROM array to return incorrect data when 

read. The problem will only occur if all of the following conditions 

are met: 



1) S bit in the CCR register is cleared (stop mode enabled) 

2) I bit in the CCR register is cleared (interrupts enabled) 

3) A STOP instruction is executed by the microcontroller 

4) An interrupt becomes pending between 0 and 0.5 bus clock cycles 

after beginning of the STOP instruction execution.



In this case the microcontroller will wake-up correctly from the stop

mode, but the EEPROM array will return incorrect data when a read

operation is performed.



Access (read or write) to any of the EEPROM registers or write into the

EEPROM array (to start a command sequence) will restore the read 

access. The EEPROM will return the correct data afterwards. 

If the STOP instruction is executed while interrupts are enabled,

read or write any of the EEPROM registers after wake-up from stop mode

to ensure correct operation. Alternatively a write into the EEPROM 

array (as part of a command sequence) can be performed instead of the 

register access. 

It is possible that after the device enters Stop or Pseudo-Stop mode it

may reset rather than wake up normally upon reception of the wake-up

signal. 



CONDITIONS: 

This event will only happen provided ALL of the following conditions are

met: 

    1) Device is powered by the on-chip voltage regulator. 

    2) Device enters stop or pseudo-stop mode (see Stop mode entry

description below) 

    3) The wake-up signal is activated within a specific and very short

window (typically 11ns long, not longer than 20ns). The position of the

window varies between different devices, however it never starts sooner

than 1.6µs and never ends later than 4.7µs after the stop mode entry. 

This narrow width of the susceptible window makes the erratum unlikely

to ever show in the applications life. 



Stop or Pseudo-Stop mode entry are: 

    1) Execution of STOP instruction by the CPU (provided the S-bit in

CCR is cleared) 

NOTE: The part enters stop mode either after 12 oscillator clock cycles

with the PLL disengaged or 3 PLL clock cycles and 8 oscillator clock

cycles with the PLL engaged after the STOP command is executed. 

    2) End of XGATE thread (provided the CPU is in stop or pseudo-stop

mode) 



The incorrect behavior will never occur if ANY of the wake-up conditions

are met at the time when the stop mode entry is attempted (an enabled

interrupt is pending). 



EFFECT: 

If this incorrect behavior occurs, the device will Reset and indicate a

Low Voltage Reset (LVR) as the reset source. 

The device will operate normally after the reset.  

None. 



-- 



Asynchronous Low Voltage Resets are possible in any microcontroller

application (due to power supply drops) and the integrated LVR and LVI

features and dedicated LVR reset vector are provided to manage this fact

cleanly. For best practice, the application's software should be written

to recover from a Low Voltage Reset in a controlled manner. Software

written to deal with valid Low Voltage Resets should be implemented to

correctly manage erroneous LVR events. 



It is also be possible to avoid erroneous Low Voltage Resets from

synchronous wake-up events by configuring the application software to

ensure that the entry into stop occurs at such a time, in relation to

the wake-up event timer, that a wake-up event does not occur within

1.6µs to 4.7µs after Stop/Pseudo-Stop entry.  

When the ATD is started with write to ATDCTL5

and, which is very unusual and not necessary,

within a certain period again started with write

to ATDCTL5. The conversion will not start at all.

This does only happen if the two consecutive writes to ATDCTL5 occur 

within one "ATD clock period". An ATD clock period is defined by a full 

rollover of the ATD clock prescaler. That is for example PRS[4:0] = 2 -

> (2+1)*2 = within 6 bus cycles.

 

Only write once to ATDCTL5 when starting a conversion.



Use the recommended start and abort procedures from the Block Guide.

Section : Initialization/Application Information Subsection: Setting up

and starting an A/D conversion Subsection: Aborting an A/D conversion 

Simultaneous disarming (hardware) and arming (software) results in 

status, flag and counter register (DBGSR, DBGMFR, DBGCNT) corruption. 



Hardware disarming initiated by an internal trigger or by tracing 

completion takes 2 clock cycles. If a write to DBGC1 with the ARM bit 

set occurs in the final clock cycle of this disarming process, arming 

is suppressed but the DBGSR register is initialized to state1 and

DBGMFR/DBGCNT are initialized to zero.



The result is that the DBG module is disarmed by hardware but DBGSR 

indicates state1.



NOTE: DBGC1 is typically only written to whilst armed to set the TRIG 

bit or update the COMRV bits to map different registers to the address 

map window.



Generally during debugging, after arming the DBG module and returning 

to application code a further write access of DBGC1 over the BDM 

interface requires considerable time relative to application code 

execution, therefore in many cases the breakpoint may be reached before 

a DBGC1 update is attempted. Furthermore the probability of hitting the 

same cycle is seen to be very low.

 

If the fault condition is caused by writing to DBGC1 to set the TRIG 

bit (to request an immediate breakpoint), then the application code may 

be rerun again without the attempted setting of TRIG. The software 

trigger (TRIG) is unnecessary in any case at the same point point in 

time as an internal hardware trigger occurs.



Development tool vendors should avoid COMRV updates while the DBG is 

armed.



Users that observe the problem due to development tool COMRV updates 

can add a NOP to code and rerun to shift the disarm cycle, thereby 

preventing a collision with the COMRV updates. 

The CPU execution priority encoder evaluates taghits and then 

generates  a breakpoint if a taghit must lead to an immediate 

breakpoint as determined by the DBG module.



If the DBG module indicates that this taghit leads to an immediate 

breakpoint then the CPU loads the execution stage with SWI or BGND thus 

generating the breakpoint.



At simultaneous taghits the lowest channel has priority.

If taghits on 2 channels simultaneously, whereby the lower channel tag 

must be ignored, but the higher channel tag must cause a breakpoint, 

then the breakpoint request is erroneously missed.

Thus if channel[1:0] taghits occur simultaneously whereby channel[0] 

must be ignored but channel[1] must cause a breakpoint, then the 

breakpoint request on channel[1] is erroneously missed and no 

breakpoint generated.



The DBG module recognises the taghit and the state sequencer 

transitions accordingly. Furthermore the taghit causes the DBG module 

to request a  forced breakpoint, which means that a late CPU breakpoint 

occurs. If the tagged instruction is a single cycle instruction, the 

breakpoint occurs at the second instruction following the tagged 

instruction.  

Otherwise the breakpoint occurs at the instruction immediately 

following the tagged instruction.



This bug requires that separate tags are placed on the same 

instruction. This is not a typical case when using exact tag addresses. 

It is more relevant in debugging environments using range modes, where 

tags may cover a whole range. In this case a tagged range may cover a 

tag or another tagged range, making simultaneous taghits possible.



This is a debugging issue only. 

Do not attach multiple tags to the same exact address. 

When attaching multiple tags to the same address by overlapping tag 

ranges in range modes, or covering a tag with a tag range in range 

modes, then the missed tag can be avoided by mapping the final state

change to the lower channel number.



For example the case

Channel[0] tags a range; channel[3] tags an instruction within that 

range. 

From DBG State1 Taghit[0] leads to State2.    (DBGSCR1=$6)

From DBG State2 Taghit[3] leads to FinalState.(DBGSCR2=$5)

In State2 a simultaneous Taghit[3,0] scenario would miss the breakpoint.



This can be avoided by using the alternative DBG configuration

Channel[2] tags a range; channel[0] tags an instruction within that 

range. 

From DBG State1 Taghit[2] leads to State2.    (DBGSCR1=$3)

From DBG State2 Taghit[0] leads to FinalState.(DBGSCR2=$7) 

If a misaligned word write access is directly followed by an attempted

entry into active BDM, then the second byte access may be performed on a

different target due to the memory map switching for active BDM. 



Thus on a misaligned global store (GSTD,GSTS,GSTX,GSTY) the lower

16-bits of the global address are interpreted as a local address

for the second byte access. This can result in unintended accesses to

registers.











 









 

Avoid setting breakpoints after a GSTD.



When not debugging, remove all instances of BGND from code.











 

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a 

read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.





Details:



When any of the buffered input capture channels 0 - 3 are configured 

for buffered/queue mode  (BUFEN=1, LATQ=0) each of the channel’s input 

capture holding registers and each channel’s associated pulse 

accumulator and its holding register are enabled. When the input 

capture channel is enabled by writing to a channel’s EDGxB and EDGxA 

bits, both the input capture and input capture holding register are 

considered empty. The first valid edge received after enabling a 

channel will latch the ECT’s free running counter into the input 

capture register (TCx) without setting the channel’s associated CxF 

interrupt flag. The second valid edge received will transfer the value 

of the input capture register, TCx, into the channel’s TCxH holding 

register, latch the current value of the free running timer into the 

input capture register and set the channel’s associated CxF interrupt 

flag. In this condition, both the TCx and TCxH registers are 

considered ‘full’.



If a corresponding channel’s NOVWx bit in the ICOVW register is set, 

the capture register or its holding register cannot be written by a 

valid edge at the input pin unless they are first emptied by reading 

the TCx and TCxH registers. The act of reading the TCx and TCxH 

registers and clearing the channel’s associated CxF interrupt flag 

involves three separate operations. Two 16-bit read operations and an 8-

bit write operation.



If a channel’s associated CxF interrupt flag is cleared before reading 

the TCx and TCxH registers and if a valid input edge occurs during or 

between the reading of the capture and holding register, a channel’s 

associated CxF interrupt flag will no longer be set as the result of 

valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx <----+

    |         |

    |<--------+--- Valid Input Edge Occurs

    V         |

Read TCxH <---+



If the TCx and TCxH registers are read before a channel’s associated 

CxF interrupt flag is cleared and if a valid input edge occurs between 

the reading of TCx/TCxH and the clearing of a channel’s associated CxF 

interrupt flag, a channel’s associated CxF interrupt flag will no 

longer be set as the result of valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx 

    |

    |<------------ Valid Input Edge Occurs

    V

Read TCxH





Systems that service the interrupt request and read the TCx and TCxH 

registers before the next valid edge occurs at a channel’s associated 

input pin will avoid the conditions under which the errata will occur.  

A simple workaround exists for this errata:



1. Clear the input capture channel’s associated CxF bit.

2. Disable the input capture function by writing 0:0 to a

   channel’s EDGxB and EDGxA bits.

3. Read TCx

4. Read TCxH

5. Re-enable the input capture function by writing to a channel’s EDGxB 

   and EDGxA bits.





Code Example:



unsigned char ICSave;

unsigned int TC0Val;

unsigned int TC0HVal;



ICSave = TCTL4 & 0x03;  /* save state of EDG0B and EDG0A */

TFLG1 = 0x01;           /* clear ECT Channel 0 flag */

TCTL4 &= 0xfc;          /* disable Channel 0 input capture function */

TC0Val = TC0;           /* Read value of TC0 */

TC0HVal = TC0H;         /* Read value of TC0H */

TCTL4 |= ICSave;        /* Restore Channel 0 input capture function */ 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 02.05 (04

 May 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.







 

If S12X is running at a bus clock frequency higher than the oscillator

clock frequency (Fbus > Fosc), flash words may remain not programmed

after a program burst sequence. Software methods can be used to avoid

this problem. If burst programming is not used, no errors occur. 



The root cause of this issue is related to flash internal state machine

which needs about 2 to 3 oscillator clock periods to be ready to accept

a new flash command after the assertion of the CBEIF flag. 



Note that this latency of flash state machine is related to the

assertion of CBEIF and the start of a new command sequence (i.e. a write

to a flash word). There is no latency after the assertion of the CCIF flag. 



 

Adding a time delay between the check of CBEIF flag and the start of the

next flash program command sequence will ensure that all words will be

programmed. Add a delay of (3 * (Fbus/Fosc)) Bus clock cycles after

CBEIF is set, that can be achieved by the addition of NOPs (one NOP

instruction takes one bus cycle to execute). 



Note that since a flash word program operation takes much longer than 3

oscillator clock periods, there is no impact in the total programming

time of a long program burst sequence by adding a delay of 3 clocks.



The example below illustrates the proposed workaround:

 

Code below executes a program burst sequence by launching a new flash

program command right after the assertion of the CBEIF flag.





1    LDX     #(PGM_ADDR_START+PGM_SIZE) ;Load X with last addr+1

2    STX     TMP_VAR                    ;Store last programmed addr+1 at

tmp_w1 var

3    LDX     #PGM_ADDR_START            ;Load X with start addr

4

5  LOOPGM:                              ;Loop Program

6    BRCLR   FSTAT, #$80, *             ;Wait for buffer empty (CBEIF = 1)

7

8    ; -> Time delay of 3 Osc clock periods must be inserted at this point.

9

10   MOVW    #DATA      2,X+           ;Write DATA to address pointed by

index X

11   MOVB    #FCMD_PGM  FCMD           ;Write PGM command code to FCMD

register

12   MOVB    #$80       FSTAT          ;Launch command   

13   CPX     TMP_VAR

14   BLO     LOOPGM

 

  The minimum time delay for the code above can be found by the equation

below:

 

  Time delay (in Bus clock cycles) =   3*(Fbus/Fosc) - (bus clock cycles

need by BRCLR at line 6) - (bus clock cycles needed by MOVW at line 10)

 

  Considering that the BRCLR instruction at line 6 takes 3 bus clock

cycles after the assertion of the CBEIF and that the MOVW takes 3 bus

clock cycles to be executed, the equation above can be written as:

 

  Time delay (in Bus clock cycles) =   3*(Fbus/Fosc) - 6

 

  For the case of Fosc=4MHz and Fbus=12MHz, a time delay of

3*(12MHz/4MHz) - 6 = 3 bus clock periods is needed. So, at least 3 NOP

instructions must be inserted at line 8 for proper operation, in this

example.



  Depending on the configuration of Bus clock frequency and oscillator

clock frequency, and due to the actual code used in the application, the

required time delay of 3 oscillator clock cycles may be already spent

inside of the programming routine and the problem will not be detected.

Under certain conditions described by the equations and explanation

above, adding NOPs may not be required.



 

When executing a flash erase verify (0x05) command sequence to a flash 

block different from the block where the backdoor keys are written to, 

both blocks will be erase verified. Any programmed location in either 

block will terminate the operation preventing the FSTAT.BLANK flag from 

setting.



When executing a flash data compress (0x06) command sequence to a flash 

block different from the block where the backdoor keys are written to, 

a given number of words from both blocks will be compressed, this 

number will be equal to the value written at last key’s address. The 

signature from the block containing the backdoor keys will affect the 

signature returned in the FDATA register.



When executing a flash program (0x20) command sequence to a flash block 

different from the block where the backdoor keys are written to, both 

blocks will be programmed at the same relative address with the 

unselected block being programmed to a data value equal to the last key 

written. Setting protection at the location in the block where the 

backdoor keys are written will not prevent the flash command from 

executing.



When executing a flash sector erase (0x40) command sequence to a flash 

block different from the block where the backdoor keys are written to, 

both blocks will receive the erase at the sector address provided in 

the flash sector erase command sequence. Setting protection in the 

location where the backdoor keys are written to will not prevent the 

flash command from executing.



When executing a flash mass erase (0x41) command sequence to a flash 

block different from the block where the backdoor keys are written to, 

both blocks will be erased. Setting protection in the block where the 

backdoor keys are written to will not prevent the flash command from 

executing.



The flash sector erase abort (0x47) command is not impacted as all 

active sector erase operations will be terminated if successfully 

aborted. 

Write 0x30 to FSTAT register (ACCERR = 1, PVIOL = 1) prior to 

executing any flash command sequence when backdoor keys have been 

written. This step can be done in conjunction with or instead of 

checking the FSTAT register as shown in the flash command sequence 

flow in the reference manual. 

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two 

cases:    



Case 1: due to re-sync of the RXD input, the received edge may be 

delayed by one bus cycle. If an edge (bit = '0') is detected near 

an SCI clock edge, the next edge (bit = '0') may be detected one 

SCI clock later than expected due to re-sync logic. 



Case 2: if external baud is slower than SCI receiver, the next edge 

may be detected later than expected.



This glitch can be detected by the RXEDGIF circuit, but it does not 

impact the final data result because the SCI receive and data recovery 

logic takes samples at RT8, RT9, and RT10.

 



 

Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit 

faster than receiver baud by:

                 P > (1/16)/(SBR)

                        or

                 (P)(SBR)(16)> 1



Where SBR is baud of receiver, P is external baud faster ratio. 

For example:

1.- When SBR = 16, P = 0.4%, this means the external baud should be at 

least 0.4% faster than receiver.

2.- When SBR = 4, P = 1.6%, this means the external baud should be at 

least 1.6% faster than receiver.

 

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is 

solved, case 2 is also solved.