Simultaneous disarming (hardware) and arming (software) results in 

status, flag and counter register (DBGSR, DBGMFR, DBGCNT) corruption. 



Hardware disarming initiated by an internal trigger or by tracing 

completion takes 2 clock cycles. If a write to DBGC1 with the ARM bit 

set occurs in the final clock cycle of this disarming process, arming 

is suppressed but the DBGSR register is initialized to state1 and

DBGMFR/DBGCNT are initialized to zero.



The result is that the DBG module is disarmed by hardware but DBGSR 

indicates state1.



NOTE: DBGC1 is typically only written to whilst armed to set the TRIG 

bit or update the COMRV bits to map different registers to the address 

map window.



Generally during debugging, after arming the DBG module and returning 

to application code a further write access of DBGC1 over the BDM 

interface requires considerable time relative to application code 

execution, therefore in many cases the breakpoint may be reached before 

a DBGC1 update is attempted. Furthermore the probability of hitting the 

same cycle is seen to be very low.

 

If the fault condition is caused by writing to DBGC1 to set the TRIG 

bit (to request an immediate breakpoint), then the application code may 

be rerun again without the attempted setting of TRIG. The software 

trigger (TRIG) is unnecessary in any case at the same point point in 

time as an internal hardware trigger occurs.



Development tool vendors should avoid COMRV updates while the DBG is 

armed.



Users that observe the problem due to development tool COMRV updates 

can add a NOP to code and rerun to shift the disarm cycle, thereby 

preventing a collision with the COMRV updates. 

The CPU execution priority encoder evaluates taghits and then 

generates  a breakpoint if a taghit must lead to an immediate 

breakpoint as determined by the DBG module.



If the DBG module indicates that this taghit leads to an immediate 

breakpoint then the CPU loads the execution stage with SWI or BGND thus 

generating the breakpoint.



At simultaneous taghits the lowest channel has priority.

If taghits on 2 channels simultaneously, whereby the lower channel tag 

must be ignored, but the higher channel tag must cause a breakpoint, 

then the breakpoint request is erroneously missed.

Thus if channel[1:0] taghits occur simultaneously whereby channel[0] 

must be ignored but channel[1] must cause a breakpoint, then the 

breakpoint request on channel[1] is erroneously missed and no 

breakpoint generated.



The DBG module recognises the taghit and the state sequencer 

transitions accordingly. Furthermore the taghit causes the DBG module 

to request a  forced breakpoint, which means that a late CPU breakpoint 

occurs. If the tagged instruction is a single cycle instruction, the 

breakpoint occurs at the second instruction following the tagged 

instruction.  

Otherwise the breakpoint occurs at the instruction immediately 

following the tagged instruction.



This bug requires that separate tags are placed on the same 

instruction. This is not a typical case when using exact tag addresses. 

It is more relevant in debugging environments using range modes, where 

tags may cover a whole range. In this case a tagged range may cover a 

tag or another tagged range, making simultaneous taghits possible.



This is a debugging issue only. 

Do not attach multiple tags to the same exact address. 

When attaching multiple tags to the same address by overlapping tag 

ranges in range modes, or covering a tag with a tag range in range 

modes, then the missed tag can be avoided by mapping the final state

change to the lower channel number.



For example the case

Channel[0] tags a range; channel[3] tags an instruction within that 

range. 

From DBG State1 Taghit[0] leads to State2.    (DBGSCR1=$6)

From DBG State2 Taghit[3] leads to FinalState.(DBGSCR2=$5)

In State2 a simultaneous Taghit[3,0] scenario would miss the breakpoint.



This can be avoided by using the alternative DBG configuration

Channel[2] tags a range; channel[0] tags an instruction within that 

range. 

From DBG State1 Taghit[2] leads to State2.    (DBGSCR1=$3)

From DBG State2 Taghit[0] leads to FinalState.(DBGSCR2=$7) 

If a misaligned word write access is directly followed by an attempted

entry into active BDM, then the second byte access may be performed on a

different target due to the memory map switching for BDM active. 



Depending on the type of access this can lead to the following situations...

1. When writing in the address range from $7F_FEFF to $7F_FFFD in the

external space the MMC splits the accesses into two 8-bit accesses. It

is able to complete the first access, but just before the second access

the BDM firmware becomes mapped into this address location and the

second byte access goes to the firmware.

This can only occur if the last cycle of the access instruction is a

word write to an odd address AND the instruction is followed by BGND or

a tagged breakpoint. 



This can only occur on devices featuring an External Bus Interface.



2. On a misaligned word write with a global store (GSTD,GSTS,GSTX,GSTY)

in the address range $XX_0FFF to $XX_3FFD, the first split access is

performed correctly in the external space, but in the second byte cycle

the MMC is instructed to interpret the address coming from the CPU as a

local address, which is the internal RAM. Since accesses to the RAM are

not split, the MMC enters an inconsistent state and never acknowledges

the CPU access. This causes the CPU flow to cease.

This can only occur if the CPU executes a global store instruction which

writes to an odd address in the last instruction cycle AND the

instruction is followed by BGND or a tagged breakpoint.



This can only occur on devices featuring an External Bus Interface.



3. Generally on a misaligned global store (GSTD,GSTS,GSTX,GSTY) the

lower 16-bits of the global address are interpreted as a local address

for the second byte access. This can result result in unintended

accesses to registers or external RAM.



 







 

Do not set breakpoints or insert BGND after a GSTD.



Remove all instances of BGND from code when not debugging.









 

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function

available on the related pin can take control over the data direction.

This does not lead to a problem if input mode is maintained. If the

alternative function switches to output mode the shutdown function may

unintentionally be triggered by the output data.

 

When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input. 



In the case that this pin is selected as an output or where an

alternative function is enabled which could drive it as an output,

enable PWM channel 7 by setting the PWME7 bit. This prevents an

active shutdown level driven on the (output) pin from resulting in an

emergency shutdown of the enabled PWM channels.

 

Where the IRQ interrupt is being used in edge-sensitive mode and a 

lower priority interrupt is already pending when an IRQ edge event 

occurs, if the IRQ edge event occurs inside a very narrow (<3ns) window 

just as the pending interrupt vector is being fetched, then a different 

vector other than that relating to either the pending interrupt or IRQ 

will be taken.

 

In the case that a programmed interrupt vector is fetched both the 

originally pending interrupt and the IRQ interrupt request will remain 

pending and will be serviced once the erroneously called service 

routine has completed (and RTI has been executed).



In the case that the incorrect vector fetch is from an unprogrammed 

vector table entry (i.e. erased state = 0xFFFF) then erroneous 

execution from the start of the register space will occur most often 

resulting in an illegal memory access reset, COP reset or Unimplemented 

Instruction Trap occurring. 



In the less likely case that one of the three reset vectors is 

incorrectly fetched then execution will jump to the appropriate reset 

code.  



The following vectors are not affected will not cause erroneous 

behavior if pending: 

$F0 - RTI

$F6 - SWI

$E2 – ECT channel 6

$B2 – CAN0 Rx

$72 – XGATE software trigger 0



This issue is limited to the edge-sensitive mode of the IRQ input only -

 applications not using IRQ interrupts or configured for level-

sensitive IRQ input are not affected.



There is no issue where a pending interrupt has higher priority than 

the IRQ request. 

Where using IRQ in edge-sensitive mode then configure the interrupt 

priority levels of all interrupts being used to ensure that the IRQ 

request always has the lowest priority. 



For new designs, where possible use the IRQ input in level-sensitive 

mode or alternatively use a key-interrupt port. 



There are a number of ‘best practices’ and features of the S12X which 

can help minimize the impact of this errata in the case of it occurring:



1) As ‘best practice’ initialize all unused and unimplemented/reserved 

interrupt vector table locations to point to a dummy interrupt service 

routine (terminated with an RTI). 



2) Where possible, check for appropriate asserted flags in interrupt 

service routines and return / flag a system error if no request flag is 

set.



3) Support is provided on the MCU for managing the following system 

conditions:

* COP watchdog reset 

* Illegal access reset 

* Unimplemented instruction trap

For ‘best practice’ the application's software should be written to 

recover from any of these conditions in a controlled manner. 



4) In the case of erroneous code execution jumping to unused Flash the 

typical practice of filling all unused Flash and RAM space with the op-

code for the SWI instruction will help manage this. SWI exception 

routine should be written in this case to manage this event.

 

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a 

read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.





Details:



When any of the buffered input capture channels 0 - 3 are configured 

for buffered/queue mode  (BUFEN=1, LATQ=0) each of the channel’s input 

capture holding registers and each channel’s associated pulse 

accumulator and its holding register are enabled. When the input 

capture channel is enabled by writing to a channel’s EDGxB and EDGxA 

bits, both the input capture and input capture holding register are 

considered empty. The first valid edge received after enabling a 

channel will latch the ECT’s free running counter into the input 

capture register (TCx) without setting the channel’s associated CxF 

interrupt flag. The second valid edge received will transfer the value 

of the input capture register, TCx, into the channel’s TCxH holding 

register, latch the current value of the free running timer into the 

input capture register and set the channel’s associated CxF interrupt 

flag. In this condition, both the TCx and TCxH registers are 

considered ‘full’.



If a corresponding channel’s NOVWx bit in the ICOVW register is set, 

the capture register or its holding register cannot be written by a 

valid edge at the input pin unless they are first emptied by reading 

the TCx and TCxH registers. The act of reading the TCx and TCxH 

registers and clearing the channel’s associated CxF interrupt flag 

involves three separate operations. Two 16-bit read operations and an 8-

bit write operation.



If a channel’s associated CxF interrupt flag is cleared before reading 

the TCx and TCxH registers and if a valid input edge occurs during or 

between the reading of the capture and holding register, a channel’s 

associated CxF interrupt flag will no longer be set as the result of 

valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx <----+

    |         |

    |<--------+--- Valid Input Edge Occurs

    V         |

Read TCxH <---+



If the TCx and TCxH registers are read before a channel’s associated 

CxF interrupt flag is cleared and if a valid input edge occurs between 

the reading of TCx/TCxH and the clearing of a channel’s associated CxF 

interrupt flag, a channel’s associated CxF interrupt flag will no 

longer be set as the result of valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx 

    |

    |<------------ Valid Input Edge Occurs

    V

Read TCxH





Systems that service the interrupt request and read the TCx and TCxH 

registers before the next valid edge occurs at a channel’s associated 

input pin will avoid the conditions under which the errata will occur.  

A simple workaround exists for this errata:



1. Clear the input capture channel’s associated CxF bit.

2. Disable the input capture function by writing 0:0 to a channel’s 

   EDGxB and EDGxA bits.

3. Read TCx

4. Read TCxH

5. Re-enable the input capture function by writing to a channel’s EDGxB 

   and EDGxA bits.





Code Example:



unsigned char ICSave;

unsigned int TC0Val;

unsigned int TC0HVal;



ICSave = TCTL4 & 0x03;  /* save state of EDG0B and EDG0A */

TFLG1 = 0x01;           /* clear ECT Channel 0 flag */

TCTL4 &= 0xfc;          /* disable Channel 0 input capture function */

TC0Val = TC0;           /* Read value of TC0 */

TC0HVal = TC0H;         /* Read value of TC0H */

TCTL4 |= ICSave;        /* Restore Channel 0 input capture function */ 

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7

(note:PWMRSTRT should be set) the PWM channels do

not show the state which is set by PWMLVL bit when the 16-bit counter is

non-zero. 





 

If emergency shutdown mode is required:



In 16-bit concatenation mode, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.



 

In low power modes (P-STOP/STOP/WAIT mode) and during PWM7

de-assert and when PWM counter reaching 0, the PWM channel outputs  

cannot keep the state which is set by PWMLVL bit.  









 

Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.









 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision V03.08 (04

 May 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.







 

If the PLL is manually turned off (PLLCTL_ PLLON = 0) before a STOP

instruction and the PLL is manually turned on (PLLCTL_PLLON=1) after

execution of the STOP instruction, the PLL might have a premature lock

condition in the case of a STOP instruction being executed with a

pending interrupt and the corresponding interrupt is enabled. In this

case the STOP is executed similar to NOP instruction. 



Due to the manual control of the PLL, the VCO clock is switched on and

off. The PLL lock detection logic uses the VCO clock as well as the

reference clock (based on the external oscillator). The external

oscillator is not stopped because the STOP instruction is executed like

a NOP instruction, which keeps the reference clock running. 



This causes the logic in the PLL lock detection being uncorrelated and

thus resulting in a possible premature LOCK condition (CRGFLG_LOCK=1). 



After the next lock detection cycle the lock is lost (CRGFLG_LOCK=0)

because the VCO clock frequency has not reached the correct value. Some

lock detection cycles later the correct lock condition is reached (VCO

clock frequency reached the correct value) and the LOCK bit is set again

(CRGFLG_LOCK=1). Each transition of the LOCK bit is indicated by the

lock interrupt flag (CRGFLG_LOCKIF). 

Do not modify the PLLON bit around the STOP instruction. 



The clock control and power down/up sequencing is automatically done by

the device CRG module. Only the system clock source selection after exit

from STOP must be controlled by software (CLKSEL_PLLSEL bit) as

described in the Reference Manual. 



Depending on the application if the fast wake-up feature is used the

software also needs to control the bit FSTWKP and bit SCME (both located

in the PLLCTL register) as described in the device Reference Manual when

STOP Mode is entered or exited.





 

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two 

cases:    



Case 1: due to re-sync of the RXD input, the received edge may be 

delayed by one bus cycle. If an edge (bit = '0') is detected near 

an SCI clock edge, the next edge (bit = '0') may be detected one 

SCI clock later than expected due to re-sync logic. 



Case 2: if external baud is slower than SCI receiver, the next edge 

may be detected later than expected.



This glitch can be detected by the RXEDGIF circuit, but it does not 

impact the final data result because the SCI receive and data recovery 

logic takes samples at RT8, RT9, and RT10.

 



 

Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit 

faster than receiver baud by:

                 P > (1/16)/(SBR)

                        or

                 (P)(SBR)(16)> 1



Where SBR is baud of receiver, P is external baud faster ratio. 

For example:

1.- When SBR = 16, P = 0.4%, this means the external baud should be at 

least 0.4% faster than receiver.

2.- When SBR = 4, P = 1.6%, this means the external baud should be at 

least 1.6% faster than receiver.

 

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is 

solved, case 2 is also solved.