NXP® Semiconductors | MSE9S12XDG128_0M42E |
Mask Set Errata | Rev. April 17, 2012 |
MC9S12XDG128, Mask 0M42E |
This errata sheet applies to the following devices: MC9S12XDG128, MC9S12XD128, MC9S12XA128, MC9S12XB128 |
The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code. |
Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002. |
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. |
MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum. |
Errata Number | Module affected | Brief Description | Work- around |
MUCts03017 | ect_16b8c | ECT: TCNT counter resets in Input Capture Mode | YES |
MUCts03018 | ect_16b8c | ECT: CxF flag clears following a read to TCx on an OC event with TFFCA=1 | YES |
MUCts03019 | ect_16b8c | ECT: CxF flag clears following a wite to TCx on an IC event with TFFCA=1 | YES |
MUCts03037 | ect_16b8c | ECT: Forced OC on PT7 occured even when TIOS7 = 0 | NO |
MUCts03039 | ect_16b8c | ECT:Faulty OC event with OM/OL=0, OC7Mx=1, TIOSx=1 | YES |
MUCts03267 | s12x_cpu | S12X_CPU : CALL Instruction, wrong PC relative addressing | YES |
MUCts03301 | s12x_cpu | S12X_CPU: CPU ignores tag hit | NO |
MUCts03315 | s12x_dbg | DBG writing to DBGMFR corrupts DBGSCR3 | YES |
MUCts03316 | s12x_dbg | DBG outside range mode databus qualification ignored | YES |
MUCts03320 | s12x_dbg | DBG Range Mode TAGB and TAGD influence in range modes | YES |
MUCts03337 | s12x_cpu | DBG Wrong trace buffer entries during stretched bus cycles | NO |
MUCts03390 | atd_10b16c | ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work | YES |
MUCts03521 | ftx_128k1 | FTX: Blind Spot in Data Compress Command Algorithm | YES |
MUCts03564 | mscan | MSCAN: Corrupt ID may be sent in early-SOF condition | YES |
MUCts03618 | s12x_dbg | DBG No address match if next transaction is misaligned word access | YES |
MUCts03619 | s12x_dbg | DBG Pure PC mode too many trace buffer entries | NO |
MUCts03635 | eetx_2k | eetx2k An interrupt following immediately after execution of a STOP instruction may disable read access to the EEPROM array | YES |
MUCts03653 | vreg_3v3 | vreg_3v3.05.02: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry | NO |
MUCts03689 | atd_10b16c | ADC: conversion does not start with 2 consecutive writes to ATDCTL5 | YES |
MUCts03758 | s12x_dbg | DBG: State flags and counter corrupted by simultaneous arm and disarm | YES |
MUCts03869 | s12x_cpu | CPU: Breakpoint missed at simultaneous taghits | YES |
MUCts03951 | s12x_bdm | BDM: Incomplete Memory Access on misaligned access due to BDM features | YES |
MUCts03977 | pwm_8b8c | PWM: Emergency shutdown input can be overruled | YES |
MUCts04040 | ftx_128k1 | FTX_128k1 : An interrupt occurring at the end of execution of a STOP instruction may cause an erroneous interrupt vector to be taken | YES |
MUCts04080 | pim_9xd_g128 | PIM: Edge-sensitive mode of IRQ-pin may cause incorrect interrupt vector fetch | YES |
MUCts04095 | ect_16b8c | ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | YES |
MUCts04135 | pwm_8b8c | PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | YES |
MUCts04136 | pwm_8b8c | PWM: Wrong output value after restart from stop or wait mode | YES |
MUCts04155 | ect_16b8c | ECT_16B8C: Output compare pulse is inaccurate | YES |
MUCts04165 | ftx_128k1 | Flash: Burst programming issue if bus clock frequency is higher than oscillator clock frequency | YES |
MUCts04244 | sci | SCI: RXEDGIF occurs more times than expected in IR mode | YES |
ECT: TCNT counter resets in Input Capture Mode | MUCts03017 |
Normal Operation: |
Reseting Free Running Counter alias Timer Counter can be avoided by |
ECT: CxF flag clears following a read to TCx on an OC event with TFFCA=1 | MUCts03018 |
Problem: |
Customer should avoid reading TCx register following an Ouput Compare event. |
ECT: CxF flag clears following a wite to TCx on an IC event with TFFCA=1 | MUCts03019 |
Normal Operation: |
Customer should avoid writing to TCx register following an Input Capture |
ECT: Forced OC on PT7 occured even when TIOS7 = 0 | MUCts03037 |
Correct Operation: |
None. |
ECT:Faulty OC event with OM/OL=0, OC7Mx=1, TIOSx=1 | MUCts03039 |
Correct Operation: |
Make sure that OC7Mx bit is set to "0" if not using OC7M feature for |
S12X_CPU : CALL Instruction, wrong PC relative addressing | MUCts03267 |
The effective address calculated by the CALL instruction using PC |
Take into account the extra constant offsets when using PC relative |
S12X_CPU: CPU ignores tag hit | MUCts03301 |
Under the following condition, the CPU ignores a tag hit and executes |
None. |
DBG writing to DBGMFR corrupts DBGSCR3 | MUCts03315 |
Writing to the read only register DBGMFR actually performs a write |
Do not write to the read only register DBGMFR. |
DBG outside range mode databus qualification ignored | MUCts03316 |
When using a comparator pair for a range comparison, the databus can |
Using 2 comparator pairs configured for inside range mode an outside |
DBG Range Mode TAGB and TAGD influence in range modes | MUCts03320 |
The comparator A and C TAG bits are used to tag range comparisons for |
Clear TAGB when configured for forced range mode comparisons using CompAB |
DBG Wrong trace buffer entries during stretched bus cycles | MUCts03337 |
This is a debug issue only. |
None. |
ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work | MUCts03390 |
Starting a conversion with a write to ATDxCTL5 or on an external trigger |
Only write to ATDxCTL4 to abort an ongoing conversion sequence. |
FTX: Blind Spot in Data Compress Command Algorithm | MUCts03521 |
If the range of Flash addresses to be compressed is 32K or greater, the |
Limit range of addresses to be compressed to less than 32K addresses. |
MSCAN: Corrupt ID may be sent in early-SOF condition | MUCts03564 |
The initial eight ID bits will be corrupted if a message is set up for |
Due to increased oscillator tolerance a transmission start in the third |
DBG No address match if next transaction is misaligned word access | MUCts03618 |
Memory accesses in successive bus cycles must both be able to generate |
Insert a NOP instruction before misaligned word accesses if they can |
DBG Pure PC mode too many trace buffer entries | MUCts03619 |
If configured for Pure PC mode tracing then an extra, unexpected trace |
None. |
eetx2k An interrupt following immediately after execution of a STOP instruction may disable read access to the EEPROM array | MUCts03635 |
An interrupt request immediately following execution of a STOP |
If the STOP instruction is executed while interrupts are enabled, |
vreg_3v3.05.02: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry | MUCts03653 |
It is possible that after the device enters Stop or Pseudo-Stop mode it |
None. |
ADC: conversion does not start with 2 consecutive writes to ATDCTL5 | MUCts03689 |
When the ATD is started with write to ATDCTL5 |
Only write once to ATDCTL5 when starting a conversion. |
DBG: State flags and counter corrupted by simultaneous arm and disarm | MUCts03758 |
Simultaneous disarming (hardware) and arming (software) results in |
If the fault condition is caused by writing to DBGC1 to set the TRIG |
CPU: Breakpoint missed at simultaneous taghits | MUCts03869 |
The CPU execution priority encoder evaluates taghits and then |
Do not attach multiple tags to the same exact address. |
BDM: Incomplete Memory Access on misaligned access due to BDM features | MUCts03951 |
If a misaligned word write access is directly followed by an attempted |
Avoid setting breakpoints after a GSTD. |
PWM: Emergency shutdown input can be overruled | MUCts03977 |
If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM |
When using the PWM emergency shutdown feature the GPIO function on the |
FTX_128k1 : An interrupt occurring at the end of execution of a STOP instruction may cause an erroneous interrupt vector to be taken | MUCts04040 |
An active interrupt request at the end of execution of a STOP |
1) A software solution is possible by ensuring that the appropriate |
PIM: Edge-sensitive mode of IRQ-pin may cause incorrect interrupt vector fetch | MUCts04080 |
Where the IRQ interrupt is being used in edge-sensitive mode and a |
Where using IRQ in edge-sensitive mode then configure the interrupt |
ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | MUCts04095 |
Channel 0 3 Input Capture interrupts are inhibited when BUFEN=1, |
A simple workaround exists for this errata: |
PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | MUCts04135 |
When the PWM is used in 16-bit (concatenation) channel and the emergency |
If emergency shutdown mode is required: |
PWM: Wrong output value after restart from stop or wait mode | MUCts04136 |
In low power modes (P-STOP/STOP/WAIT mode) and during PWM7 |
Before entering low power modes, user can disable the related PWM |
ECT_16B8C: Output compare pulse is inaccurate | MUCts04155 |
The pulse width of an output compare (which resets the free running |
The specification has been updated. Please refer to revision 02.05 (04 |
Flash: Burst programming issue if bus clock frequency is higher than oscillator clock frequency | MUCts04165 |
If S12X is running at a bus clock frequency higher than the oscillator |
Adding a time delay between the check of CBEIF flag and the start of the |
SCI: RXEDGIF occurs more times than expected in IR mode | MUCts04244 |
Configured for Infrared Receive mode, the SCI may incorrectly set the |
Case 1 and case 2 may occurs at same time. To avoid those unexpected |