NXP® Semiconductors | MSE9S12UF32_1L79R |
Mask Set Errata | Rev. April 17, 2012 |
MC9S12UF32, Mask 1L79R |
This errata sheet applies to the following devices: MC9S12UF32 |
The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code. |
Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002. |
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. |
MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum. |
Errata Number | Module affected | Brief Description | Work- around |
MUCts00755 | S12_bdm | BDM: ACK conflict exiting STOP | YES |
MUCts00762 | S12_cpu | DBG: CPU erroneously causes BSRs to be recorded in trace buffer | YES |
MUCts01008 | fts32k | Array writes immediately after FPROT write do not set PVIOL flag. | YES |
MUCts01050 | fts32k | Flash: ACCERR is not set for a Byte Access | YES |
MUCts01051 | fts32k | STOP instruction may not set ACCERR flag | NO |
MUCts01966 | S12_bdm | Possible manipulation of return address when exiting BDM active mode | YES |
MUCts02415 | S12_mebi | MEBI: Missing ECLK edge on first external access after mode switching | YES |
MUCts04159 | tim_16b8c | TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 | YES |
MUCts04161 | tim_16b8c | TIM_16B8C: Output compare pulse is inaccurate | YES |
MUCts04248 | sci | SCI: RXEDGIF occurs more times than expected in IR mode | YES |
BDM: ACK conflict exiting STOP | MUCts00755 |
When using the Background Debugger to debug |
The ACK protocol can be disabled when debugging |
DBG: CPU erroneously causes BSRs to be recorded in trace buffer | MUCts00762 |
The BSR instruction is recognized as a change of flow instruction and |
The severity of this bug is directly related to the frequency of BSR |
Array writes immediately after FPROT write do not set PVIOL flag. | MUCts01008 |
A write to the flash protection register that is immediately followed by |
Perform a legal write of a register immediately after writing to the |
Flash: ACCERR is not set for a Byte Access | MUCts01050 |
Starting a command sequence with a MOVB array write instruction (Byte |
Avoid the use of MOVB instruction for array program operations. |
STOP instruction may not set ACCERR flag | MUCts01051 |
If a STOP instruction is issued between the time when an NVM command is |
None. |
Possible manipulation of return address when exiting BDM active mode | MUCts01966 |
Upon leaving BDM active mode, the CPU return address is stored |
Avoid using the BGND instruction when the ENBDM bit in the BDMSTS |
MEBI: Missing ECLK edge on first external access after mode switching | MUCts02415 |
If the ECLK is used as an external bus control signal (ESTR=1) the first |
Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK |
TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 | MUCts04159 |
When an OC7M bit is set, an erroneous normal output compare event can |
Set OC7Mx = 1 only for channels where the output compare action should |
TIM_16B8C: Output compare pulse is inaccurate | MUCts04161 |
The pulse width of an output compare (which resets the free running |
The specification has been updated. Please refer to revision 01.09 (07 |
SCI: RXEDGIF occurs more times than expected in IR mode | MUCts04248 |
Configured for Infrared Receive mode, the SCI may incorrectly set the |
Case 1 and case 2 may occurs at same time. To avoid those unexpected |