NXP® Semiconductors | MSE9S12UF32_0L47S |
Mask Set Errata | Rev. April 17, 2012 |
MC9S12UF32, Mask 0L47S |
This errata sheet applies to the following devices: MC9S12UF32 |
The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code. |
Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002. |
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. |
MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum. |
Errata Number | Module affected | Brief Description | Work- around |
MUCts01498 | ique | Security cannot be disabled via BDM unsecure command sequence | YES |
MUCts01659 | ata5hc | Invalid UDMA write sequence in a corner case | YES |
MUCts01665 | ique | Reset sequence in double buffer mode | YES |
MUCts01861 | S12_bdm | Possible manipulation of return address when exiting BDM active mode | YES |
MUCts02415 | S12_mebi | MEBI: Missing ECLK edge on first external access after mode switching | YES |
MUCts03031 | tim_16b8c | TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 | YES |
MUCts04160 | tim_16b8c | TIM_16B8C: Output compare pulse is inaccurate | YES |
MUCts04246 | sci | SCI: RXEDGIF occurs more times than expected in IR mode | YES |
Security cannot be disabled via BDM unsecure command sequence | MUCts01498 |
When security is enabled (MCU is reset with bits[1:0] of the flash |
Do not enable security by leaving bits[1:0] of the flash security byte |
Invalid UDMA write sequence in a corner case | MUCts01659 |
An invalid UDMA write sequence exists under a specific condition: |
Monitor the IQUE buffer in software and swap buffer resources out if |
Reset sequence in double buffer mode | MUCts01665 |
The default reset state for the read/write enable signal of the FSM |
Change the QCnREQ value to $FF before resetting the IQUE module or |
Possible manipulation of return address when exiting BDM active mode | MUCts01861 |
Upon leaving BDM active mode, the CPU return address is stored |
Avoid using the BGND instruction when the ENBDM bit in the BDMSTS |
MEBI: Missing ECLK edge on first external access after mode switching | MUCts02415 |
If the ECLK is used as an external bus control signal (ESTR=1) the first |
Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK |
TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 | MUCts03031 |
When an OC7M bit is set, an erroneous normal output compare event can |
Set OC7Mx = 1 only for channels where the output compare action should |
TIM_16B8C: Output compare pulse is inaccurate | MUCts04160 |
The pulse width of an output compare (which resets the free running |
The specification has been updated. Please refer to revision 01.05 (05 |
SCI: RXEDGIF occurs more times than expected in IR mode | MUCts04246 |
Configured for Infrared Receive mode, the SCI may incorrectly set the |
Case 1 and case 2 may occurs at same time. To avoid those unexpected |