When using the Background Debugger to debug 

code which contains STOP instructions, the 

host debugger can lose clock sync with the

target device. If the ACK protocol is enabled,

a target command which is expecting to send

and ACK pulse, can conflict with a host issued

SYNC command attempting to re-establish clock

sync between the host and target. 

The ACK protocol can be disabled when debugging

source code which contains STOP instructions.

The host SYNC command may then be used to re-establish

clock sync between the host and target after 

a STOP instruction. 

The specified MSCAN wake-up glitch filter pulse limits can be exceeded.

At low temp/high VDD the module may wake up from sleep mode on glitches

<2us while for pulses >5us it may not wake up from sleep mode at high

temp/low VDD.



The device operates at relaxed limits:



MSCAN Wake-up dominant pulse filtered: max. 1us

MSCAN Wake-up dominant pulse pass:     min. 7us

 

None.

The specified maximum pulse width limit of the key wake-up glitch filter

may be exceeded during high temperature and low supply voltage

conditions. The MCU may not wake from STOP mode on pulses slightly

greater than or equal to 10us. 

The glitch filter now operates at a maximum pulse width limit of 14us.

Ensure that valid MCU wake pulses have a duration of at least 14us. 

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed

normally programming the array according to the content (word) of the

data register while only the high byte in the FDATA register holds valid

information.  

Avoid the use of MOVB instruction for array program operations.  

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is

set), the execution of a STOP instruction will erroneously set the

ACCERR access error bit in the FSTAT flash status register. 

The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded. 

A write to the flash protection register that is immediately followed by

a flash array write will not set the PVIOL protection violation flag.



Example: 

 MOVB #$FB FPROT     //protect lower portion of flash page $3E 

 STD #$55AA #$8080   //write to protected address (PVIOL flag expected,

but does not occur) 

Perform a legal write of a register immediately after writing to the

FPROT register, before writing to the flash array.



Example: 

MOVB #$FB FPROT    //protect lower portion of flash page $3E 

MOVB #$30 FSTAT    //clear error flags (legal write to register) 

STD #$55AA #$8080  //write to protected address (PVIOL flag sets to show

protection violation) 

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command

transmission is detected during this time, the return address will be

manipulated in the BDM shift register. This situation is likely to occur

when a CPU BGND instruction is executed in user code during debugging

under the following conditions:



(i) The BDM module is not enabled AND

(ii) BDM commands are sent from the host



If this situation occurs, the CPU will execute BDM firmware and will

check the status of the ENBDM bit in the BDMSTS register. If the BDM is

disabled, the ENBDM bit will be clear, and hence the BDM firmware will

be exited and the shift register manipulation described above will occur. 

Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared. 

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with

enabled ECLK output to an expanded mode. The ECLK is erroneously held in

the high phase thus the first external bus access does not generate a

rising ECLK edge for the external logic to latch the address. The ECLK

stretches low after the lost access resulting in all following external

accesses to be valid. 

Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access. 

When an OC7M bit is set, an erroneous normal output compare event can 

happen on a timer port if the compare action is selected as "Timer 

disconnected from output pin logic ".

 

Corresponding configuration:

*  TIOSx = 1 --> Output compare mode

*  OMx = OLx = 0 --> Output compare logic disconnected from the pin

*  OC7Mx = 1 --> Mask bit set for OC7 event











 

Set OC7Mx = 1 only for channels where the output compare action should 

drive the pin, and OC7Mx = 0 for all other channels where the pin is 

required to be disconnected from the output compare logic. 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 01.09 (07

May 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.











 

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two 

cases:    



Case 1: due to re-sync of the RXD input, the received edge may be 

delayed by one bus cycle. If an edge (bit = '0') is detected near 

an SCI clock edge, the next edge (bit = '0') may be detected one 

SCI clock later than expected due to re-sync logic. 



Case 2: if external baud is slower than SCI receiver, the next edge 

may be detected later than expected.



This glitch can be detected by the RXEDGIF circuit, but it does not 

impact the final data result because the SCI receive and data recovery 

logic takes samples at RT8, RT9, and RT10.

 



 

Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit 

faster than receiver baud by:

                 P > (1/16)/(SBR)

                        or

                 (P)(SBR)(16)> 1



Where SBR is baud of receiver, P is external baud faster ratio. 

For example:

1.- When SBR = 16, P = 0.4%, this means the external baud should be at 

least 0.4% faster than receiver.

2.- When SBR = 4, P = 1.6%, this means the external baud should be at 

least 1.6% faster than receiver.

 

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is 

solved, case 2 is also solved.