NXP® Semiconductors | MSE9S12T64_0L42M |
Mask Set Errata | Rev. February 13, 2011 |
MC9S12T64, Mask 0L42M |
This errata sheet applies to the following devices: MC9S12T64 |
The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code. |
Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002. |
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. |
MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum. |
Errata Number | Module affected | Brief Description | Work- around |
MUCts00708 | spi | SPTEF flag set erroneously | YES |
MUCts00732 | sram2k | RESET asserted during RAM read access may disturb RAM contents | NO |
MUCts00738 | atd_10b8c | flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set | YES |
MUCts00742 | spi | SPI in Mode Fault state, but MISO output buffer not disabled. | NO |
MUCts00756 | util | MSCAN: Glitch filter exceeds spec limits | NO |
MUCts00757 | util | Key wake-up: Glitch filter exceeds upper 10us limit | YES |
MUCts00762 | S12_cpu | DBG: CPU erroneously causes BSRs to be recorded in trace buffer | YES |
MUCts00789 | atd_10b8c | Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags | YES |
MUCts00799 | spi | MISO not kept after sixteenth SCK edge. | YES |
MUCts00820 | crg | PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset | YES |
MUCts00825 | fts64k2 | STOP instruction may set flash ACCERR flag. | YES |
MUCts00860 | fts64k2 | Flash: ACCERR is not set for a Byte Access | YES |
MUCts01011 | ect_16b8c | ECT: Input pulse shorter than delay counter period recognised as a valid | YES |
MUCts01037 | atd_10b8c | CCF flags in ATDSTAT1 register might fail to set | NO |
MUCts01040 | atd_10b8c | ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work | YES |
MUCts01053 | spi | SPIDR can be written without reading SPTEF flag as set | YES |
MUCts02415 | S12_mebi | MEBI: Missing ECLK edge on first external access after mode switching | YES |
MUCts03474 | atd_10b8c | ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work | YES |
MUCts03682 | atd_10b8c | ADC: conversion does not start with 2 consecutive writes to ATDCTL5 | YES |
MUCts04073 | pwm_8b8c | PWM: Emergency shutdown input can be overruled | YES |
MUCts04108 | ect_16b8c | ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | YES |
MUCts04151 | ect_16b8c | ECT_16B8C: Output compare pulse is inaccurate | YES |
MUCts04199 | pwm_8b8c | PWM: Wrong output value after restart from stop or wait mode | YES |
MUCts04203 | pwm_8b8c | PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | YES |
SPTEF flag set erroneously | MUCts00708 |
When the SPI is enabled in master mode, with CPHA bit set, back to back |
After the SPTEF flag has been set, a delay of 1/2 SCK period has to be |
RESET asserted during RAM read access may disturb RAM contents | MUCts00732 |
If the RESET pin is asserted (pulled low) during a RAM read access the |
None |
flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set | MUCts00738 |
For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that |
SCF |
SPI in Mode Fault state, but MISO output buffer not disabled. | MUCts00742 |
When the SPI is in Mode Fault state (MODF flag set), according to the |
None. |
MSCAN: Glitch filter exceeds spec limits | MUCts00756 |
The specified MSCAN wake-up glitch filter pulse limits can be exceeded. |
None. |
Key wake-up: Glitch filter exceeds upper 10us limit | MUCts00757 |
The specified maximum pulse width limit of the key wake-up glitch filter |
The glitch filter now operates at a maximum pulse width limit of 14us. |
DBG: CPU erroneously causes BSRs to be recorded in trace buffer | MUCts00762 |
The BSR instruction is recognized as a change of flow instruction and |
The severity of this bug is directly related to the frequency of BSR |
Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags | MUCts00789 |
If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing |
to abort a ongoing conversion use the recommended |
MISO not kept after sixteenth SCK edge. | MUCts00799 |
In SPI slave mode with CPHA set, MISO can change erroneously after a |
There are two possible workarounds for this problem: |
PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset | MUCts00820 |
This Erratum applies only to systems where PLL is used to divide down |
1) Avoid osc_clock/pll_clock ratios between 2 and 3. |
STOP instruction may set flash ACCERR flag. | MUCts00825 |
If the FCLKDIV flash clock divider register has been loaded, and the |
The ACCERR bit in the FSTAT register must be cleared after the execution |
Flash: ACCERR is not set for a Byte Access | MUCts00860 |
Starting a command sequence with a MOVB array write instruction (Byte |
Avoid the use of MOVB instruction for array program operations. |
ECT: Input pulse shorter than delay counter period recognised as a valid | MUCts01011 |
According to the observation, input pulse (high/low) whose pulse width |
A software workaround is available. |
CCF flags in ATDSTAT1 register might fail to set | MUCts01037 |
The setting of the CCF7-0 flags in ATDSTAT1 register |
None. |
ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work | MUCts01040 |
Starting a new conversion by writing to the ATDCTL5 register should |
If the unexpected setting of one CCF flag can not be |
SPIDR can be written without reading SPTEF flag as set | MUCts01053 |
On the first instance after MCU reset, the SPIDR data register can be |
Do not attempt to write the SPIDR data register without first checking |
MEBI: Missing ECLK edge on first external access after mode switching | MUCts02415 |
If the ECLK is used as an external bus control signal (ESTR=1) the first |
Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK |
ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work | MUCts03474 |
Starting a conversion with a write to ATDxCTL5 or on an external |
Only write to ATDxCTL4 to abort an ongoing conversion sequence. |
ADC: conversion does not start with 2 consecutive writes to ATDCTL5 | MUCts03682 |
When the ATD is started with write to ATDCTL5 |
Only write once to ATDCTL5 when starting a conversion. |
PWM: Emergency shutdown input can be overruled | MUCts04073 |
If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM |
When using the PWM emergency shutdown feature the GPIO function on the |
ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | MUCts04108 |
Channel 0 3 Input Capture interrupts are inhibited when BUFEN=1, |
A simple workaround exists for this errata: |
ECT_16B8C: Output compare pulse is inaccurate | MUCts04151 |
The pulse width of an output compare (which resets the free running |
The specification has been updated. Please refer to revision 01.06 (28 |
PWM: Wrong output value after restart from stop or wait mode | MUCts04199 |
In low power modes (stop/p-stop/wait PSWAI=1) and during PWM PP7 |
Before entering low power modes, user can disable the related PWM |
PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | MUCts04203 |
When the PWM is used in 16-bit (concatenation) channel and the emergency |
If emergency shutdown mode is required: |