NXP® Semiconductors | MSE9S12T64_0L24K |
Mask Set Errata | Rev. February 13, 2011 |
MC9S12T64, Mask 0L24K |
This errata sheet applies to the following devices: MC9S12T64 |
The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code. |
Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002. |
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. |
MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum. |
Errata Number | Module affected | Brief Description | Work- around |
MUCts00468 | S12_bkp | Breakpoint Module: potential extraneous data match | NO |
MUCts00589 | ect_16b8c | ECT: can't use channel 0-3 for OC if queuing is enabled | YES |
MUCts00703 | spi | SPIDR is writeable though the SPTEF flag is cleared. | YES |
MUCts00707 | spi | SPTEF flag set erroneously | YES |
MUCts00729 | mcu_9t64 | S12_mebi: Missing external ECLK during reset vector fetch | NO |
MUCts00731 | fts64k2 | Program & Erase of flash blocked in Normal Single Chip Mode when secure | YES |
MUCts00739 | atd_10b8c | flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set | YES |
MUCts00743 | spi | SPI in Mode Fault state, but MISO output buffer not disabled. | NO |
MUCts00762 | S12_cpu | DBG: CPU erroneously causes BSRs to be recorded in trace buffer | YES |
MUCts00790 | atd_10b8c | Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags | YES |
MUCts00798 | spi | MISO not kept after sixteenth SCK edge. | YES |
MUCts00811 | ect_16b8c | ECT: Input pulse shorter than delay counter period recognised as a valid | YES |
MUCts00817 | crg | PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset | YES |
MUCts00826 | fts64k2 | STOP instruction may set flash ACCERR flag. | YES |
MUCts00859 | fts64k2 | Flash: ACCERR is not set for a Byte Access | YES |
MUCts01030 | atd_10b8c | CCF flags in ATDSTAT1 register might fail to set | NO |
MUCts01041 | atd_10b8c | ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work | YES |
MUCts01532 | ect_16b8c | ECT_16B8C: Output compare pulse is inaccurate | YES |
MUCts02415 | S12_mebi | MEBI: Missing ECLK edge on first external access after mode switching | YES |
MUCts04073 | pwm_8b8c | PWM: Emergency shutdown input can be overruled | YES |
MUCts04109 | ect_16b8c | ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | YES |
MUCts04199 | pwm_8b8c | PWM: Wrong output value after restart from stop or wait mode | YES |
MUCts04203 | pwm_8b8c | PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | YES |
Breakpoint Module: potential extraneous data match | MUCts00468 |
When using the breakpoint in full mode, there is a chance of a false |
ECT: can't use channel 0-3 for OC if queuing is enabled | MUCts00589 |
When using one or more of channels 0-3 as output compare, while using |
If a customer wants to use less than the maximum of 4 Input capture |
SPIDR is writeable though the SPTEF flag is cleared. | MUCts00703 |
Data can be placed into the SPI Data Register (SPIDR) even though the |
Do not write to the SPI Data Register until you have |
SPTEF flag set erroneously | MUCts00707 |
When the SPI is enabled in master mode, with CPHA bit set, back to back |
After the SPTEF flag has been set, a delay of 1/2 SCK period has to be |
S12_mebi: Missing external ECLK during reset vector fetch | MUCts00729 |
The reset conditions of the ECLK control logic in the MEBI |
None. |
Program & Erase of flash blocked in Normal Single Chip Mode when secure | MUCts00731 |
In normal single chip mode, when security is enabled, it is not |
To enable the Program ($20), Sector-Erase ($40) |
flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set | MUCts00739 |
For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that |
SCF |
SPI in Mode Fault state, but MISO output buffer not disabled. | MUCts00743 |
When the SPI is in Mode Fault state (MODF flag set), according to the |
None. |
DBG: CPU erroneously causes BSRs to be recorded in trace buffer | MUCts00762 |
The BSR instruction is recognized as a change of flow instruction and |
The severity of this bug is directly related to the frequency of BSR |
Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags | MUCts00790 |
If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing |
1. Make sure the device is protected from interrupts (temporarily |
MISO not kept after sixteenth SCK edge. | MUCts00798 |
In SPI slave mode with CPHA set, MISO can change erroneously after a |
There are two possible workarounds for this problem: |
ECT: Input pulse shorter than delay counter period recognised as a valid | MUCts00811 |
According to the observation, input pulse (high/low) whose pulse width |
A software workaround is available. |
PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset | MUCts00817 |
This Erratum applies only to systems where PLL is used to divide down |
1) Avoid osc_clock/pll_clock ratios between 2 and 3. |
STOP instruction may set flash ACCERR flag. | MUCts00826 |
If the FCLKDIV flash clock divider register has been loaded, and the |
The ACCERR bit in the FSTAT register must be cleared after the execution |
Flash: ACCERR is not set for a Byte Access | MUCts00859 |
Starting a command sequence with a MOVB array write instruction (Byte |
Avoid the use of MOVB instruction for array program operations. |
CCF flags in ATDSTAT1 register might fail to set | MUCts01030 |
The setting of the CCF7-0 flags in ATDSTAT1 register |
None. |
ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work | MUCts01041 |
Starting a new conversion by writing to the ATDCTL5 register should |
If the unexpected setting of one CCF flag can not be |
ECT_16B8C: Output compare pulse is inaccurate | MUCts01532 |
The pulse width of an output compare (which resets the free running |
The specification has been updated. Please refer to revision 01.06 (28 |
MEBI: Missing ECLK edge on first external access after mode switching | MUCts02415 |
If the ECLK is used as an external bus control signal (ESTR=1) the first |
Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK |
PWM: Emergency shutdown input can be overruled | MUCts04073 |
If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM |
When using the PWM emergency shutdown feature the GPIO function on the |
ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 | MUCts04109 |
Channel 0 3 Input Capture interrupts are inhibited when BUFEN=1, |
A simple workaround exists for this errata: |
PWM: Wrong output value after restart from stop or wait mode | MUCts04199 |
In low power modes (stop/p-stop/wait PSWAI=1) and during PWM PP7 |
Before entering low power modes, user can disable the related PWM |
PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode | MUCts04203 |
When the PWM is used in 16-bit (concatenation) channel and the emergency |
If emergency shutdown mode is required: |