When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.



When a transmission completes and a further byte is available in the SPI

Data Register, the second transmission begins direclty after "minimum

trailing time".



The problem occurs, when after the SPTEF flag has been set a further

byte is written into the SPI Data Register during the "1st pulse" of a

subsequent transmission.



                                            |--> next tx 

            7th pulse       8th pulse       1st pulse 

 SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______



 SPTEF _____________________________________|^^|____|^^^^^^^^

                                            ^  ^    ^

                                            |  |    |

                                            |  |   SPTEF flag set again

                                            |  |   (WRONG)

                                            |  | 

                                            |  Write to SPIDR during

                                            |  "1st pulse"

                                            |

                                            End of tx SPTEF flag is

                                            set



Then the SPTEF flag is set at the falling SCK edge of the "1st

pulse" and data is transfered from the SPI Data Register to the transmit

shift register. The result is that the transmission is corrupted. 

 

After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added before storing data into the SPI Data Register.

 

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.

Writing '1' to the respective flag has no effect. 



The ETORF flag is also set by a non-active edge, e.g. falling edge

trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and

rising edges while conversion is in progress. 

SCF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL5 (a new conversion sequence is started) 

        b. If AFFC=1 a result register is read 

ETORF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence

           is aborted) 

        b. Write to ATDCTL5 (a new conversion sequence is started) 

2. Avoid external trigger edges during conversion process by using short

pulses 

3. Ignore ETROF flag 



FIFOR 

1. Use the alternative flag clearing mechanism: 

        a. Start a new conversion sequence

           (write to ATDCTL5 or external trigger) 

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be

disabled. However, the MISO output buffer is not disabled.

 

None.

When using the Background Debugger to debug 

code which contains STOP instructions, the 

host debugger can lose clock sync with the

target device. If the ACK protocol is enabled,

a target command which is expecting to send

and ACK pulse, can conflict with a host issued

SYNC command attempting to re-establish clock

sync between the host and target. 

The ACK protocol can be disabled when debugging

source code which contains STOP instructions.

The host SYNC command may then be used to re-establish

clock sync between the host and target after 

a STOP instruction. 

The specified MSCAN wake-up glitch filter pulse limits can be exceeded.

At low temp/high VDD the module may wake up from sleep mode on glitches

<2us while for pulses >5us it may not wake up from sleep mode at high

temp/low VDD.



The device operates at relaxed limits:



MSCAN Wake-up dominant pulse filtered: max. 1us

MSCAN Wake-up dominant pulse pass:     min. 7us

 

None.

The specified maximum pulse width limit of the key wake-up glitch filter

may be exceeded during high temperature and low supply voltage

conditions. The MCU may not wake from STOP mode on pulses slightly

greater than or equal to 10us. 

The glitch filter now operates at a maximum pulse width limit of 14us.

Ensure that valid MCU wake pulses have a duration of at least 14us. 

If there are two or more buffers set up with the same identifier, message

transmission takes place until the first buffer with the matching identifier has

transmitted its message. All subsequent buffers with lower priority identifiers

are blocked from transmission for the remaining duration of this communication

cycle. 

None.

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)

ASCIF flags remain set and are NOT cleared by a write to ATDCTL5 

1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).

2. Write to ATDCTL5 twice.  

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK

edge. This can lead to a hold time violation on the SPI master.





 

There are two possible workarounds for this problem: 



   1. Decrease the bus clock of the slave SPI to satisfy the "Master 

      MISO Hold Time". 

      Tbus(Slave) >= 0.5 * "Master MISO Hold Time"



   2. Software workaround: 

      The slave has to transmit a dummy byte after each data byte, 

      which must fulfil the following requirements: 



      - The first bit of the dummy byte to be transmitted (depending on 

        LSBFE bit) must be equal to the last bit of the data byte 

        transmitted before. The dummy byte has to be stored into SPIDR 

        during the transmission of the corresponding data byte. 

        => MISO does not change after the data byte.

 

      - The Master has to receive two bytes, the data byte and the dummy 

        byte.

        => Master receives the data byte correctly and has to skip the 

           dummy byte. 

The Receive FIFO Not Empty Interrupt Flag is not cleared immediately

after the FIFO has been emptied and buffer 0 is unlocked. 

Software needs to consider at least a latency of 5 osc clocks + 1 bus

clock before reading the flag. 

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.



If



1) pll_clock (PLLON=1) is running

and

2) 2 < osc_clock/pll_clock < 3

and

3) full stop mode is entered (STOP instruction with PSTP Bit =0) 



there is a small possibility that when entering full stop mode the chip 

reacts as follows:

1) if self clock mode is disabled (SCME=0)  monitor reset is asserted.

   The system does NOT enter stop mode.

or

2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)

   a self clock mode interrupt is generated. The SCMIF flag is set.

   The system does NOT enter stop mode.

or

3) if  SCME=1 and SCMIE=0 the system will enter full stop mode. 

   But after wakeup self clock mode is entered without doing the 

   specified clock quality check. The SCMIF flag is set. 

1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or

2) if you really require osc_clock/pll_clock ratio between 2 and 3

do the following before going into stop.

a) deselect PLL (PLLSEL=0)

b) turn off PLL (PLLON=0)

c) enter stop

d) exiting stop: turn on PLL again (PLLON=1) 

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed

normally programming the array according to the content (word) of the

data register while only the high byte in the FDATA register holds valid

information.  

Avoid the use of MOVB instruction for array program operations. 

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed

normally programming the array according to the content (word) of the

data register while only the high byte in the FDATA register holds valid

information. 

Avoid the use of MOVB instruction for array program operations.  

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is

set), the execution of a STOP instruction will erroneously set the

ACCERR access error bit in the FSTAT flash status register. 

The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded. 

If the ECLKDIV EEPROM clock divider register has been loaded, and the

EEPROM is not executing a command (EEPROM CCIF command complete flag is

set), the execution of a STOP instruction will erroneously set the

ACCERR access error bit in the ESTAT EEPROM status register. 

The ACCERR bit in the ESTAT register must be cleared after the execution

of a STOP instruction if the ECLKDIV register has been loaded. 

According to the observation, input pulse (high/low) whose pulse width

is shorter than delay counter window is mistakenly recognized as as

valid pulse. Hence the ic flags will be set and may result in an IRQ if

IRQ is enabled. 



 

A software workaround is available.



User software should check the logic level of the input capture pin 

within the interrupt service routine and compare this with the logic 

level when the input is not asserted. This can be performed using the 

appropriate registers in the port integration module.



If the pin reads the logic level of the inactive state, the pulse is 

shorter than the time defined in the delay counter control register 

plus the interrupt latency. In this case, the pulse triggering the 

input capture is not valid (too short), hence the interrupt can be 

acknowledged and exited without further action taking place. If the pin 

reads the logic level of the active state, the input pulse is valid and 

the interrupt should be acknowledged and the correct input capture 

service routine executed.



The effectiveness of this workaround must be evaluated by identifying

the worst case latency involved in the call of the ISR. To maximise the

effectiveness of pulse rejection, users must consider checking the 

value in the capture register against the free-running timer on every 

new capture. 

The setting of the CCF7-0 flags in ATDSTAT1 register

is not independent of the clearing. 

A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)

which occurs in exactly the same bus cycle as the setting of any other

flag CCFy (x,y = 0,1,..,7; x!=y) masks the setting of CCFy.

CCFy will not set in this special case although the corresponding

conversion has completed and the result (ATDDRy) is valid. 

None.

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.

This does not always work if the write to ATDCTL5 register

occurs near the end of an ongoing conversion.

Although all CCF flags are cleared one CCF flag might be

set again within the 1st ATD clock period of the new conversion. 

If the unexpected setting of one CCF flag can not be

accepted by the application one of the following

workarounds can be taken:

1) Abort conversion (e.g. by write to ATDCTL3)

   Pause for 2 ATD clock periods

   Start new conversion

2) Ignore first conversion sequence and clear CCF flags

 

On the first instance after MCU reset, the SPIDR data register can be

written without reading the SPISR status register with the SPTEF

transmit buffer empty flag set. This is contrary to the specification

which states that writes to the SPIDR are ignored if the SPISR is not

previously read as being set. 

Do not attempt to write the SPIDR data register without first checking

the SPTEF transmit buffer empty flag as set. 

When the foreground receive buffer (RxFG) is read, with the Receiver

Full Flag (RXF) set, the value of the Time Stamp Register may be

incorrect due to corruption. The Time Stamp Register is written

correctly when the message is received, but may be overwritten by the

timer value at the end of a subsequent reception. The corruption can

only occur close to a data overrun, when the receive buffer FIFO is

full.



The problem occurs whenever the following two conditions are met: 



1. Receive buffer system is full 

All five receive buffers contain valid messages waiting to be read by

the application. 



2. Another valid message is seen on the bus. This message must be sent

from another node, i.e. it must not be transmitted from the respective

msCAN module itself. 



At the end of the message in 2. the Time Stamp Register of the oldest

message in the receive FIFO is overwritten. 



Note: if the message in 2. passes the message filter system the Overrun

Interrupt Flag (OVRIF) is also set. 

The application software has to ensure to read the receive messages in

due time to avoid data overrun in any case. This will automatically

minimize the risk of a Time Stamp Register overwrite event. 

If a particular error condition occurs within the end of frame segment

(EOF) of a CAN message, the msCAN module recognises and accepts a

non-valid message as being valid, contrary to the CAN specification. The

msCAN module incorrectly validates messages after five recessive bits of

the end of frame instead of after six bits. If a bus error occurs during

the sixth bit of end of frame, the msCAN module will already have

accepted the message as valid, even although an error frame is

transmitted and the receive error counter is incremented.



The CAN protocol states that message validation differs between bus

transmitter and receiver devices (refer to part B, section 5 of CAN

protocol for details). In the case where the 7th bit of the EOF segment

is dominant, the message is valid for the receiver but not for the

transmitter. This erratum extends this case to the 6th bit of the EOF

segment. 

This erratum will not be an issue if the application software is

protected against the known double receive problem of the CAN protocol.

This problem occurs when a message is not recognised as valid by the

transmitter, but is recognised as valid by a receiver, as described

above. When this happens, the message is re-transmitted and hence the

receiver will receive the same message twice.

 

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command

transmission is detected during this time, the return address will be

manipulated in the BDM shift register. This situation is likely to occur

when a CPU BGND instruction is executed in user code during debugging

under the following conditions:



(i) The BDM module is not enabled AND

(ii) BDM commands are sent from the host



If this situation occurs, the CPU will execute BDM firmware and will

check the status of the ENBDM bit in the BDMSTS register. If the BDM is

disabled, the ENBDM bit will be clear, and hence the BDM firmware will

be exited and the shift register manipulation described above will occur. 

Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared. 

At oscillator frequencies above 4MHz the Program step of the EEPROM

Sector-Modify command can fail depending on the bus frequency. As a

result, no programming of the EEPROM occurs. There is no impact to the

Erase step of the Sector-Modify command. Since a partial programming of

the word cannot occur, there is not a reliability issue caused by the

Sector-Modify command if the programmed word is verified.

 

   Oscillator             Bus

   Frequency           Frequency

   ----------    ----------------------

     4MHz             No Issue

     8MHz        Fbus <20MHz : No issue

    16MHz        Fbus <16MHz : No issue





 

Use seperate Erase and Program commands in place of the Sector-Modify

command. If the Sector-Modify command is used and fails the program step

as confirmed by a user verification step, a Program command alone can be

used to effectively complete the operation since the erase step does

successfully erase the sector. 

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with

enabled ECLK output to an expanded mode. The ECLK is erroneously held in

the high phase thus the first external bus access does not generate a

rising ECLK edge for the external logic to latch the address. The ECLK

stretches low after the lost access resulting in all following external

accesses to be valid. 

Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access. 

Starting a conversion with a write to ATDxCTL5 or on an external 

trigger event, and aborting immediately afterwards with a write to 

ATDxCTL0, ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the 

conversion process.





 

Only write to ATDxCTL4 to abort an ongoing conversion sequence.



Use the recommended start and abort procedures from the Block Guide.

Section :  Initialization/Application Information

Subsection: Setting up and starting an A/D conversion

Subsection: Aborting an A/D conversion





 

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is

sampled leading to an early-SOF*.



The CRC is calculated from the resulting bit stream so that the

receiving nodes will still validate the message.



An early-SOF condition may only occur if the oscillators in the network

operate at a tolerance range which could lead to a cumulated phase error

after 11 bit times larger than phase segment 2. 



In case arbitration is lost during transmission of the corrupt

identifier, a non-corrupted ID will be sent with the next attempt if the

transmit request remains active.



*The CAN protocol condition referred to as 'early-SOF' in this erratum

is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,

and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B. 

Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided

when calculating the maximum oscillator tolerance of the overall CAN

system. The phase error after 11 bit times due to the oscillator

tolerance should be smaller than phase segment 2.



If an early-SOF cannot be avoided the following methods will provide

prevention:



- Assigning the same value to all upper eight ID bits in the network

- Allocating dedicated data length codes (DLC) to every identifier used 

  in the network and checking for correspondence after reception

- Assigning only IDs (x) which do not consist of a combination of other 

  assigned IDs (y,z) and using the acceptance filters to reject 

  erroneous messages, i.e. 

  - for standard frames: IDx[11:0]  != {IDy[11:3], IDz[2:0]}

  - for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]} 

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function

available on the related pin can take control over the data direction.

This does not lead to a problem if input mode is maintained. If the

alternative function switches to output mode the shutdown function may

unintentionally be triggered by the output data.

 

When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input. 



In the case that this pin is selected as an output or where an

alternative function is enabled which could drive it as an output,

enable PWM channel 7 by setting the PWME7 bit. This prevents an

active shutdown level driven on the (output) pin from resulting in an

emergency shutdown of the enabled PWM channels.

 

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a 

read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.





Details:



When any of the buffered input capture channels 0 - 3 are configured 

for buffered/queue mode  (BUFEN=1, LATQ=0) each of the channel’s input 

capture holding registers and each channel’s associated pulse 

accumulator and its holding register are enabled. When the input 

capture channel is enabled by writing to a channel’s EDGxB and EDGxA 

bits, both the input capture and input capture holding register are 

considered empty. The first valid edge received after enabling a 

channel will latch the ECT’s free running counter into the input 

capture register (TCx) without setting the channel’s associated CxF 

interrupt flag. The second valid edge received will transfer the value 

of the input capture register, TCx, into the channel’s TCxH holding 

register, latch the current value of the free running timer into the 

input capture register and set the channel’s associated CxF interrupt 

flag. In this condition, both the TCx and TCxH registers are 

considered ‘full’.



If a corresponding channel’s NOVWx bit in the ICOVW register is set, 

the capture register or its holding register cannot be written by a 

valid edge at the input pin unless they are first emptied by reading 

the TCx and TCxH registers. The act of reading the TCx and TCxH 

registers and clearing the channel’s associated CxF interrupt flag 

involves three separate operations. Two 16-bit read operations and an 8-

bit write operation.



If a channel’s associated CxF interrupt flag is cleared before reading 

the TCx and TCxH registers and if a valid input edge occurs during or 

between the reading of the capture and holding register, a channel’s 

associated CxF interrupt flag will no longer be set as the result of 

valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx <----+

    |         |

    |<--------+--- Valid Input Edge Occurs

    V         |

Read TCxH <---+



If the TCx and TCxH registers are read before a channel’s associated 

CxF interrupt flag is cleared and if a valid input edge occurs between 

the reading of TCx/TCxH and the clearing of a channel’s associated CxF 

interrupt flag, a channel’s associated CxF interrupt flag will no 

longer be set as the result of valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx 

    |

    |<------------ Valid Input Edge Occurs

    V

Read TCxH





Systems that service the interrupt request and read the TCx and TCxH 

registers before the next valid edge occurs at a channel’s associated 

input pin will avoid the conditions under which the errata will occur.  

A simple workaround exists for this errata:



1. Clear the input capture channel’s associated CxF bit.

2. Disable the input capture function by writing 0:0 to a channel’s 

   EDGxB and EDGxA bits.

3. Read TCx

4. Read TCxH

5. Re-enable the input capture function by writing to a channel’s EDGxB 

   and EDGxA bits.





Code Example:



unsigned char ICSave;

unsigned int TC0Val;

unsigned int TC0HVal;



ICSave = TCTL4 & 0x03;  /* save state of EDG0B and EDG0A */

TFLG1 = 0x01;           /* clear ECT Channel 0 flag */

TCTL4 &= 0xfc;          /* disable Channel 0 input capture function */

TC0Val = TC0;           /* Read value of TC0 */

TC0HVal = TC0H;         /* Read value of TC0H */

TCTL4 |= ICSave;        /* Restore Channel 0 input capture function */ 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 01.06 (28

 Apr 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.







 

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs

(PP0-PP6) cannot keep the state which is set by PWMLVL bit.  



 

Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.

 

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7

(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the

state which is set by PWMLVL bit when the 16-bit counter is non-zero. 

 

If emergency shutdown mode is required:



In 16-bit concatenation mode, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.