A write to the flash protection register that is immediately followed by

a flash array write will not set the PVIOL protection violation flag.



Example: 

 MOVB #$FB FPROT      //protect lower portion of flash page $3E 

 STD  #$55AA #$8080   //write to protected address (PVIOL flag expected,

but does not occur) 

Perform a legal write of a register immediately after writing to the

FPROT register, before writing to the flash array.



Example: 

MOVB #$FB FPROT    //protect lower portion of flash page $3E 

MOVB #$30 FSTAT    //clear error flags (legal write to register) 

STD #$55AA #$8080  //write to protected address (PVIOL flag sets to show

protection violation) 

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.

This does not always work if the write to ATDCTL5 register

occurs near the end of an ongoing conversion.

Although all CCF flags are cleared one CCF flag might be

set again within the 1st ATD clock period of the new conversion. 

If the unexpected setting of one CCF flag can not be

accepted by the application one of the following

workarounds can be taken:

1) o Abort conversion (e.g. by write to ATDCTL3)

   o pause for 2 ATD clock periods

   o Start new conversion

2) o ignore first conversion sequence and clear CCF flags 

When the foreground receive buffer (RxFG) is read, with the Receiver

Full Flag (RXF) set, the value of the Time Stamp Register may be

incorrect due to corruption. The Time Stamp Register is written

correctly when the message is received, but may be overwritten by the

timer value at the end of a subsequent reception. The corruption can

only occur close to a data overrun, when the receive buffer FIFO is

full.



The problem occurs whenever the following two conditions are met: 



1. Receive buffer system is full 

All five receive buffers contain valid messages waiting to be read by

the application. 



2. Another valid message is seen on the bus. This message must be sent

from another node, i.e. it must not be transmitted from the respective

msCAN module itself. 



At the end of the message in 2. the Time Stamp Register of the oldest

message in the receive FIFO is overwritten. 



Note: if the message in 2. passes the message filter system the Overrun

Interrupt Flag (OVRIF) is also set. 

The application software has to ensure to read the receive messages in

due time to avoid data overrun in any case. This will automatically

minimize the risk of a Time Stamp Register overwrite event. 

The errata concerns the DBG-CPU interface in DBG mode whilst configured

for tagging. If an interrupt occurs at the moment that a tag is attached

to an opcode being loaded into the instruction queue, the flag will get

set, but the part may not enter active BDM mode. 



Using the DBG configuration BDM=DBGBRK=1, BEGIN=0, an event causing a

flag to be set should cause a break to BDM. The flag gets set, but the

part does not enter active BDM mode. The CPU executes the interrupt

service routine, instead, and returns to the correct position in the

program flow, but the breakpoint to BDM is missed.



The problem does not occur if the DBG module is configured for operation

in BKP mode (BKABEN=1). This is because, even if the flag bit is set,

the BKABEN bit is not cleared. On returning from the interrupt service

routine, the tag is re-applied when the PC is fetched after the

interrupt service routine, and the part enters BDM after the interrupt

service routine. In BKP mode with TRGSEL=0, no flags are set when a

taghit occurs. 



In BKP mode with TRGSEL=1, the flag is also set erroneously on entering

the interrupt service routine. However, it is unlikely that a user would

be affected by the flag being set early (unless the service routine were

exceptionally long), due to the length of time needed to read out the

DBGSR (flag bits) over the BKGD pin; typically, during this time, the

part would enter active BDM when the tag is re-applied. 

None.

The issue occurs at system level on devices featuring crg and vreg_3v3 



During pseudo stop mode the internal logic is supplied from a low power,

backup voltage regulator.

During normal operation (RUN or WAIT modes) the internal logic is

supplied from the full performance voltage regulator.



At wake up from pseudo stop mode the internal system clocks are applied

before the voltage regulator ramp up to full performance mode is

completed. This causes a heavy load in the ramp up phase. 



As a result, the supply voltage level may not be sufficient during the

ramp up phase, leading to a system reset or code run away.

 

Do not use pseudo STOP mode. 

When the MCU returns from STOP mode, the internal VDD level can dip

below the LVR level leading to a Power On Reset (POR) event.

 

1) Do not use STOP mode.



 



 

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take

place between temperatures of -20C and 125C ambient.



In addition, the flash program times have been increased as follows:



                                                   Programming Time 

                                                    Min.      Max.

Single Word Program                      (Tswpgm)    66.0us    99.2us  

Flash Row Program - Consecutive Word     (Tbwpgm)    40.4us    57.8us

Flash Row Program - 64 words             (Tbrpgm)  2608.7us  3742.7us



Actual programming time will vary between the above bounds depending on

flash clock and bus clock frequencies.



Important Notes: 

1) Program time is internally controlled by the flash state machine. 

   No action needs to be taken by users in connection with this erratum. 

2) Both flash erase and flash read temperature specifications and 

   operation times are unaffected by this erratum.

3) EEPROM is unaffected by this erratum. 

 

None.

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.

This does not always work if the write to ATDCTL5 register

occurs near the end of an ongoing conversion.

Although all CCF flags are cleared one CCF flag might be

set again within the 1st ATD clock period of the new conversion. 

If the unexpected setting of one CCF flag can not be

accepted by the application one of the following

workarounds can be taken:

1) o Abort conversion (e.g. by write to ATDCTL3)

   o pause for 2 ATD clock periods

   o Start new conversion

2) o ignore first conversion sequence and clear CCF flags 

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command

transmission is detected during this time, the return address will be

manipulated in the BDM shift register. This situation is likely to occur

when a CPU BGND instruction is executed in user code during debugging

under the following conditions:



(i) The BDM module is not enabled AND

(ii) BDM commands are sent from the host



If this situation occurs, the CPU will execute BDM firmware and will

check the status of the ENBDM bit in the BDMSTS register. If the BDM is

disabled, the ENBDM bit will be clear, and hence the BDM firmware will

be exited and the shift register manipulation described above will occur. 

Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared. 

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with

enabled ECLK output to an expanded mode. The ECLK is erroneously held in

the high phase thus the first external bus access does not generate a

rising ECLK edge for the external logic to latch the address. The ECLK

stretches low after the lost access resulting in all following external

accesses to be valid. 

Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access. 

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low 

causes the transmit shift register to be locked for the next 

transmission following the SPI being re-enabled as a slave with SS 

still being low. 



This means new transmit data is not accepted for the first 

transmission after re-enabling the SPI (indicated by SPTEF staying low 

after storing transmit data into SPIDR), but for the next following 

transmission.



 

When disabling the slave SPI, CPHA should not be cleared at the same time. 

Starting a conversion with a write to ATDxCTL5 or on an external 

trigger event, and aborting immediately afterwards with a write to 

ATDxCTL0, ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the 

conversion process.





 

Only write to ATDxCTL4 to abort an ongoing conversion sequence.



Use the recommended start and abort procedures from the Block Guide.

Section :  Initialization/Application Information

Subsection: Setting up and starting an A/D conversion

Subsection: Aborting an A/D conversion





 

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is

sampled leading to an early-SOF*.



The CRC is calculated from the resulting bit stream so that the

receiving nodes will still validate the message.



An early-SOF condition may only occur if the oscillators in the network

operate at a tolerance range which could lead to a cumulated phase error

after 11 bit times larger than phase segment 2. 



In case arbitration is lost during transmission of the corrupt

identifier, a non-corrupted ID will be sent with the next attempt if the

transmit request remains active.



*The CAN protocol condition referred to as 'early-SOF' in this erratum

is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,

and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B. 

Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided

when calculating the maximum oscillator tolerance of the overall CAN

system. The phase error after 11 bit times due to the oscillator

tolerance should be smaller than phase segment 2.



If an early-SOF cannot be avoided the following methods will provide

prevention:



- Assigning the same value to all upper eight ID bits in the network

- Allocating dedicated data length codes (DLC) to every identifier used 

  in the network and checking for correspondence after reception

- Assigning only IDs (x) which do not consist of a combination of other 

  assigned IDs (y,z) and using the acceptance filters to reject 

  erroneous messages, i.e. 

  - for standard frames: IDx[11:0]  != {IDy[11:3], IDz[2:0]}

  - for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]} 

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function

available on the related pin can take control over the data direction.

This does not lead to a problem if input mode is maintained. If the

alternative function switches to output mode the shutdown function may

unintentionally be triggered by the output data.



 

When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input. 



In the case that this pin is selected as an output or where an

alternative function is enabled which could drive it as an output,

enable PWM channel 5 by setting the PWME5 bit. This prevents an

active shutdown level driven on the (output) pin from resulting in an

emergency shutdown of the enabled PWM channels.



 

When an OC7M bit is set, an erroneous normal output compare event can 

happen on a timer port if the compare action is selected as "Timer 

disconnected from output pin logic ".

 

Corresponding configuration:

*  TIOSx = 1 --> Output compare mode

*  OMx = OLx = 0 --> Output compare logic disconnected from the pin

*  OC7Mx = 1 --> Mask bit set for OC7 event











 

Set OC7Mx = 1 only for channels where the output compare action should 

drive the pin, and OC7Mx = 0 for all other channels where the pin is 

required to be disconnected from the output compare logic. 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 01.09 (07

May 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.











 

When the PWM is used in 16-bit (concatenation) channel and the 

emergency

shutdown feature is being used, after de-asserting PWM channel 5

(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show 

the

state which is set by PWMLVL bit when the 16-bit counter is non-zero. 



 

None. 

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs

(PP0-PP4) cannot keep the state which is set by PWMLVL bit.  





 

None.