Presented by
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Ecosystem Product Manager, NXP Semiconductors
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
PLU enables you to create small logic networks that run independently on CPU. Lower the processing load or use it during deep-sleep mode. And configuration of this peripheral is very easy!
In this course you learn how to use MCUXpresso Config tools to configure PLU via schematic design either using logic gates or look up tables, or even via Verilog source code.
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