Wireless Backhaul

Block Diagram

Wireless Backhaul

Wireless Backhaul BD

Supported Devices

Sensors

I3C/I²C Digital Temp. Sensors

Power Management

PMICs

Processors and Microcontrollers

Layerscape Processors

Features

  • Four Cortex-A72 cores, 2MB L2 cache
  • 2x 10 GbE, 1x 2.5 GbE, and 5x GbE
  • Eight-lane SerDes up to 10 GHz multiplexed across controllers supporting: Three PCI Express® Gen 2 interfaces and SATA 3.0 Interface
  • DPAA Parse, Classify and Distribution Engines
  • Integrated security engine
  • DDR4
  • 3x PCIe 3.0 Controllers, x4, x2, x1
  • 3x USB 3.0 with integrated PHY
  • SATA 3.0 controller
  • Quad SPI
  • QorIQ® Platform's Trust Architecture
  • Arm SMMU for hardware-enhanced virtualization

Documentation

Quick reference to our documentation types.

3 documents

Support

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