Secure Enclave for Asymmetric Multi-Processing | NXP Semiconductors

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Secure Enclave for Asymmetric Multi-Processing

Secure Enclave for Asymmetric Multi-Processing

About This Training

The approach to securing a device is often concentrated around having strong cryptography support. However, for IoT devices that typically are unattended and expected to function flawlessly for years, getting security right can be very challenging, especially due to a large attack surface. Building on the EdgeLock security concept, NXP next generation secure enclave aggregates a number of security relevant functions into a “security subsystem” with tight control of resources during boot and at the run-time, including start of the art support for trust provisioning. In SoC that targets low power for IoT applications can be quite complex especially when leveraging a Heterogeneous Processing architecture, and running multiple OSes. NXP’s secure enclave is power aware and enforces specific system policies to enter and exit low power modes securely, with special consideration to minimize the entry/exit times, one of the key requirements for an IoT device.

Presentation

Addressing Industrial and IoT Security with Certified Solutions from NXP

Presented by

Lawrence Case
SoC Security Architect, NXP Semiconductors
Mohit Arora
Systems Architect, NXP Semiconductors
Nicusor Penisoara
Advanced IP Enablement Lead, NXP Semiconductors

DURATION

48 min

LANGUAGE

English

SKILL LEVEL

Beginner

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