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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes default configuration structures for SPI module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
Macros | |
#define | SPI_MODULE_DIV24_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. More... | |
#define | SPI_MODULE_DIV24_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. More... | |
#define | SPI_MODULE_DIV4_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. More... | |
#define | SPI_MODULE_DIV4_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. More... | |
#define | SPI_MODULE_DIV12_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. More... | |
#define | SPI_MODULE_DIV12_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. More... | |
#define | SPI_MODULE_DIV2_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. More... | |
#define | SPI_MODULE_DIV2_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. More... | |
#define | SPI_MODULE_DIV2_16B_IRQ_CONFIG |
SPI setting in 16bit IRQ mode. More... | |
#define | SPI_MODULE_DIV2_16B_POLL_CONFIG |
SPI setting in 16bit POLLING mode. More... | |
#define | SPI_MODULE_DIV2_16B_POLL_SLAVE_FIFO_CONFIG |
SPI setting in 16bit POLLING SLAVE mode with the FIFO buffer enabled. More... | |
#define | SPI_MODULE_DIV6_16B_FIFO_SLAVE_CPHA_CONFIG |
SPI setting in 16bit FIFO SLAVE mode. More... | |
#define | SPI_MODULE_DIV6_16B_FIFO_MASTER_CPHA_CONFIG |
SPI setting in 16bit FIFO SLAVE mode. More... | |
#define | SPI_MODULE_DIV2_16B_POLL_FIFO_CONFIG |
SPI setting in 16bit POLLING mode with the FIFO buffer enabled. More... | |
#define SPI_MODULE_DIV24_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. Baud rate is 1/24 of BUSCLK, 8-bit interrupt mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV24_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. Baud rate is 1/24 of BUSCLK, 8-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV4_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. Baud rate is 1/4 of BUSCLK, 8-bit interrupt mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV4_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. Baud rate is 1/4 of BUSCLK, 8-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV12_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. Baud rate is 1/12 of BUSCLK, 8-bit interrupt mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV12_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. Baud rate is 1/12 of BUSCLK, 8-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_8B_IRQ_CONFIG |
SPI setting in 8bit IRQ mode. Baud rate is 1/2 of BUSCLK, 8-bit interrupt mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_8B_POLL_CONFIG |
SPI setting in 8bit POLLING mode. Baud rate is 1/2 of BUSCLK, 8-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_16B_IRQ_CONFIG |
SPI setting in 16bit IRQ mode. Baud rate is 1/2 of BUSCLK, 8-bit interrupt mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_16B_POLL_CONFIG |
SPI setting in 16bit POLLING mode. Baud rate is 1/2 of BUSCLK, 16-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), no FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_16B_POLL_SLAVE_FIFO_CONFIG |
SPI setting in 16bit POLLING SLAVE mode with the FIFO buffer enabled. Baud rate is 1/2 of BUSCLK, 16-bit polling mode, module enabled after initialization, slave mode, SS is configured as GPIO (must be driven manually!), enabled FIFO no DMA no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV6_16B_FIFO_SLAVE_CPHA_CONFIG |
SPI setting in 16bit FIFO SLAVE mode. Baud rate is 1/6 of BUSCLK, CPHA is enabled, 16-bit IRQ mode, module enabled after initialization, slave mode, FIFO is enabled, no DMA, no MATCH functionality, Rx FIFO near full watermark 32bit mode, Rx FIFO nearly full interrupt is enabled, full-duplex mode.
#define SPI_MODULE_DIV6_16B_FIFO_MASTER_CPHA_CONFIG |
SPI setting in 16bit FIFO SLAVE mode. Baud rate is 1/6 of BUSCLK, CPHA is enabled, 16-bit polling mode, module enabled after initialization, master mode, FIFO is enabled, no DMA, no MATCH functionality, full-duplex mode.
#define SPI_MODULE_DIV2_16B_POLL_FIFO_CONFIG |
SPI setting in 16bit POLLING mode with the FIFO buffer enabled. Baud rate is 1/2 of BUSCLK, 16-bit polling mode, module enabled after initialization, master mode, SS is configured as GPIO (must be driven manually!), enabled FIFO no DMA no MATCH functionality, full-duplex mode.