MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
FLL Bypassed Controlled by 8.0 MHz OSC

This example shows VLPR operation with core, bus and flash blocks clocked by FLL module. The FLL module is configured in Bypass Low Power External (BLPE) mode clocked by 8.0 MHz System Oscillator (OSC).

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* oscvlpr_test.c
******************************************************************************/
#include "drivers.h"
void main (void)
{
/* enable clocks to all peripherals - clock mode 2:1:1 (core:bus:flash) */
/* route bus clock to PTF7 */
/* system oscillator and FLL settings */
/* switch to VLPR mode */
SMC_SetMode(VLPR);
while(1);
}
Toolchain support:
IAR EWARM 7.40.7CodeWarrior 10.6KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0