MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
PORT Configuration Structures

Overview

This section describes default configuration structures for PORT module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure). Refer to Pin Assignments.

Macros

#define PORT_MODULE_ALT0_MODE
 Configures pin(s) to Alternative 0 (analogue) mode. Digital portion of the port pin logic is disabled. Pins with no analogue functionality as well as their internal pull-up resistors will be disabled. More...
 
#define PORT_MODULE_ALT0_PULLUP_EN_MODE
 Configures pin(s) to Alternative 0 (analogue) mode. Digital portion of the port pin logic is disabled. Pins with no analogue functionality will be disabled keeping their pull-up resistors enabled. More...
 
#define PORT_MODULE_ALT1_MODE
 Configures pin(s) to Alternative 1 (GPIO) mode. More...
 
#define PORT_MODULE_ALT1_PULLUP_EN_MODE
 Configures pin(s) to Alternative 1 (GPIO) mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT1_LOGIC0_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) IRQ when logic 0 mode. More...
 
#define PORT_MODULE_ALT1_LOGIC1_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) IRQ when logic 1 mode. More...
 
#define PORT_MODULE_ALT1_POSEDGE_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) IRQ on rising edge mode. More...
 
#define PORT_MODULE_ALT1_NEGEDGE_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) IRQ on falling edge mode. More...
 
#define PORT_MODULE_ALT1_ANYEDGE_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) IRQ on either edge mode. More...
 
#define PORT_MODULE_ALT2_MODE
 Configures pin(s) to Alternative 2 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT2_PULLUP_EN_MODE
 Configures pin(s) to Alternative 2 mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT3_MODE
 Configures pin(s) to Alternative 3 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT3_PULLUP_EN_MODE
 Configures pin(s) to Alternative 3 mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT4_MODE
 Configures pin(s) to Alternative 4 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT4_PULLUP_EN_MODE
 Configures pin(s) to Alternative 4 mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT5_MODE
 Configures pin(s) to Alternative 5 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT5_PULLUP_EN_MODE
 Configures pin(s) to Alternative 5 mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT6_MODE
 Configures pin(s) to Alternative 6 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT6_PULLUP_EN_MODE
 Configures pin(s) to Alternative 6 mode with pull-up enabled. More...
 
#define PORT_MODULE_ALT7_MODE
 Configures pin(s) to Alternative 7 (chip-specific) mode. More...
 
#define PORT_MODULE_ALT7_PULLUP_EN_MODE
 Configures pin(s) to Alternative 7 mode with pull-up enabled. More...
 
#define PORT_MODULE_BUTTON_MODE
 Configures pin(s) to Alternative 1 (GPIO) filtered mode ready for button processing using polling. More...
 
#define PORT_MODULE_BUTTON_IRQ_MODE
 Configures pin(s) to Alternative 1 (GPIO) filtered mode ready for button processing using interrupts. More...
 
#define PORT_MODULE_LED_MODE
 Configures pin(s) to Alternative 1 (GPIO) mode ready for controlling slow outputs such LEDs. More...
 

Macro Definition Documentation

#define PORT_MODULE_ALT0_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(0))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT0_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(0))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_LOGIC0_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(8))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt when logic zero enabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_LOGIC1_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(12))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt when logic one enabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_POSEDGE_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(9))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt on rising edge enabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_NEGEDGE_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(10))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt on falling edge enabled
  • Slew rate control disabled
#define PORT_MODULE_ALT1_ANYEDGE_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(11))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt on either edge enabled
  • Slew rate control disabled
#define PORT_MODULE_ALT2_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(2))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT2_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(2))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT3_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(3))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT3_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(3))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT4_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(4))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT4_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(4))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT5_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(5))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT5_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(5))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT6_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(6))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT6_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(6))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT7_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(7))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_ALT7_PULLUP_EN_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(7))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control disabled
#define PORT_MODULE_BUTTON_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ SET(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter enabled
  • Interrupt disabled
  • Slew rate control disabled
Note
Only PORTE has the digital filter feature for reduced noise and hardware switch de-bouncing. When applying this configuration on other ports the digital filter will be disabled.
#define PORT_MODULE_BUTTON_IRQ_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(10))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ CLR(PORT_PCR_SRE_MASK)|SET(PORT_PCR_PE_MASK)|SET(PORT_PCR_PS_MASK),\
/* DFER */ SET(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up enabled
  • Digital filter enabled
  • Interrupt on falling edge enabled
  • Slew rate control disabled
Note
Only PORTE has the digital filter feature for reduced noise and hardware switch de-bouncing. When applying this configuration on other ports the digital filter will be disabled.
#define PORT_MODULE_LED_MODE
Value:
(tPORT){ \
/* PCR */ SET(PORT_PCR_IRQC(0))|CLR(PORT_PCR_LK_MASK)|SET(PORT_PCR_MUX(1))| \
/* ... */ SET(PORT_PCR_SRE_MASK)|CLR(PORT_PCR_PE_MASK)|CLR(PORT_PCR_PS_MASK),\
/* DFER */ CLR(PORT_DFER_DFE_MASK), /* use mask for all pins */ \
}

Configures port pin(s) with the following characteristics:

  • Internal pull-up disabled
  • Digital filter disabled
  • Interrupt disabled
  • Slew rate control enabled