![]() |
MKMxxZxxACxx5 Bare Metal Software Drivers
R4.1.6
Reference Manual
|
This example shows FLL Engaged Internal (FEI) controlled by 32.0 kHz IRC and PLL Engaged External (PEE) clocked by 32.768 kHz RTC Oscillator. The FLL module usually generates faster clock than PLL and it is intended for driving system, core and flash blocks. The FLL can be configured in Engaged Internal (FEI) mode using 32.0 kHz IRC as the clock source. The PLL module shall be clocked by 32.768 kHz RTCOSC in order to generate a low jitter clock for Analogue Front-End (AFE) operation.
IAR EWARM 7.40.7 | CodeWarrior 10.6 | KEIL uVision 5.15 | CrossWorks 3.6 | ATOLLIC TrueStudio 5.3.0 | Kinetis Design Studio 3.0.0 |
---|---|---|---|---|---|
♦ | ♦ | ♦ | ♦ | ♦ | ♦ |