This section describes default configuration structures for UART module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define UART_MODULE_POLLMODE_CONFIG |
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brate, |
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clk |
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) |
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Value:(tUART){ \
CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
((CALC_SBR(brate,clk)>>0)&0xff), \
CLR(UART_C1_LOOPS_MASK)|
CLR(UART_C1_RSRC_MASK)| \
CLR(UART_C1_M_MASK)|
CLR(UART_C1_WAKE_MASK)| \
CLR(UART_C1_ILT_MASK)|
CLR(UART_C1_PE_MASK)| \
CLR(UART_C2_TIE_MASK)|
CLR(UART_C2_TCIE_MASK)| \
CLR(UART_C2_RIE_MASK)|
CLR(UART_C2_ILIE_MASK)| \
SET(UART_C2_TE_MASK)|
SET(UART_C2_RE_MASK)| \
CLR(UART_C2_RWU_MASK)|
CLR(UART_C2_SBK_MASK), \
CLR(UART_S2_RXEDGIF_MASK)|
CLR(UART_S2_MSBF_MASK)| \
CLR(UART_S2_RXINV_MASK)|
CLR(UART_S2_RWUID_MASK)| \
CLR(UART_S2_BRK13_MASK), \
CLR(UART_C3_T8_MASK)|
CLR(UART_C3_TXDIR_MASK)| \
CLR(UART_C3_TXINV_MASK)|
CLR(UART_C3_ORIE_MASK)| \
CLR(UART_C3_NEIE_MASK)|
CLR(UART_C3_FEIE_MASK)| \
CLR(UART_C3_PEIE_MASK), \
SET(UART_MA1_MA(0x00)), \
SET(UART_MA2_MA(0x00)), \
CLR(UART_C4_MAEN1_MASK)|
CLR(UART_C4_MAEN2_MASK)| \
CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
CLR(UART_C5_TDMAS_MASK)|
CLR(UART_C5_RDMAS_MASK) \
}
Configures UART to operate in polling mode. Receive and transmit data is not inverted.
- Parameters
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brate | Baud rate. |
clk | Module clock in Hz:
UART0 | UART1 | UART2 | UART3 |
Bus clock | System clock | Bus clock | System clock |
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#define UART_MODULE_POLLMODE_TXINV_CONFIG |
( |
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brate, |
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clk |
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) |
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Value:(tUART){ \
CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
((CALC_SBR(brate,clk)>>0)&0xff), \
CLR(UART_C1_LOOPS_MASK)|
CLR(UART_C1_RSRC_MASK)| \
CLR(UART_C1_M_MASK)|
CLR(UART_C1_WAKE_MASK)| \
CLR(UART_C1_ILT_MASK)|
CLR(UART_C1_PE_MASK)| \
CLR(UART_C2_TIE_MASK)|
CLR(UART_C2_TCIE_MASK)| \
CLR(UART_C2_RIE_MASK)|
CLR(UART_C2_ILIE_MASK)| \
SET(UART_C2_TE_MASK)|
SET(UART_C2_RE_MASK)| \
CLR(UART_C2_RWU_MASK)|
CLR(UART_C2_SBK_MASK), \
CLR(UART_S2_RXEDGIF_MASK)|
CLR(UART_S2_MSBF_MASK)| \
CLR(UART_S2_RXINV_MASK)|
CLR(UART_S2_RWUID_MASK)| \
CLR(UART_S2_BRK13_MASK), \
CLR(UART_C3_T8_MASK)|
CLR(UART_C3_TXDIR_MASK)| \
SET(UART_C3_TXINV_MASK)|
CLR(UART_C3_ORIE_MASK)| \
CLR(UART_C3_NEIE_MASK)|
CLR(UART_C3_FEIE_MASK)| \
CLR(UART_C3_PEIE_MASK), \
SET(UART_MA1_MA(0x00)), \
SET(UART_MA2_MA(0x00)), \
CLR(UART_C4_MAEN1_MASK)|
CLR(UART_C4_MAEN2_MASK)| \
CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
CLR(UART_C5_TDMAS_MASK)|
CLR(UART_C5_RDMAS_MASK) \
}
Configures UART to operate in polling mode. Receive data is not inverted. Transmit data is inverted.
- Parameters
-
brate | Baud rate. |
clk | Module clock in Hz:
UART0 | UART1 | UART2 | UART3 |
Bus clock | System clock | Bus clock | System clock |
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#define UART_MODULE_INTRMODE_CONFIG |
( |
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brate, |
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clk |
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) |
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Value:(tUART){ \
CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
((CALC_SBR(brate,clk)>>0)&0xff), \
CLR(UART_C1_LOOPS_MASK)|
CLR(UART_C1_RSRC_MASK)| \
CLR(UART_C1_M_MASK)|
CLR(UART_C1_WAKE_MASK)| \
CLR(UART_C1_ILT_MASK)|
CLR(UART_C1_PE_MASK)| \
CLR(UART_C2_TIE_MASK)|
CLR(UART_C2_TCIE_MASK)| \
SET(UART_C2_RIE_MASK)|
CLR(UART_C2_ILIE_MASK)| \
SET(UART_C2_TE_MASK)|
SET(UART_C2_RE_MASK)| \
CLR(UART_C2_RWU_MASK)|
CLR(UART_C2_SBK_MASK), \
CLR(UART_S2_RXEDGIF_MASK)|
CLR(UART_S2_MSBF_MASK)| \
CLR(UART_S2_RXINV_MASK)|
CLR(UART_S2_RWUID_MASK)| \
CLR(UART_S2_BRK13_MASK), \
CLR(UART_C3_T8_MASK)|
CLR(UART_C3_TXDIR_MASK)| \
CLR(UART_C3_TXINV_MASK)|
CLR(UART_C3_ORIE_MASK)| \
CLR(UART_C3_NEIE_MASK)|
CLR(UART_C3_FEIE_MASK)| \
CLR(UART_C3_PEIE_MASK), \
SET(UART_MA1_MA(0x00)), \
SET(UART_MA2_MA(0x00)), \
CLR(UART_C4_MAEN1_MASK)|
CLR(UART_C4_MAEN2_MASK)| \
CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
CLR(UART_C5_TDMAS_MASK)|
CLR(UART_C5_RDMAS_MASK) \
}
Configures UART to operate in interrupt mode. Receive and transmit data is not inverted.
- Parameters
-
brate | Baud rate. |
clk | Module clock in Hz:
UART0 | UART1 | UART2 | UART3 |
Bus clock | System clock | Bus clock | System clock |
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#define UART_MODULE_INTRMODE_TXINV_CONFIG |
( |
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brate, |
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clk |
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) |
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Value:(tUART){ \
CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
((CALC_SBR(brate,clk)>>0)&0xff), \
CLR(UART_C1_LOOPS_MASK)|
CLR(UART_C1_RSRC_MASK)| \
CLR(UART_C1_M_MASK)|
CLR(UART_C1_WAKE_MASK)| \
CLR(UART_C1_ILT_MASK)|
CLR(UART_C1_PE_MASK)| \
CLR(UART_C2_TIE_MASK)|
CLR(UART_C2_TCIE_MASK)| \
SET(UART_C2_RIE_MASK)|
CLR(UART_C2_ILIE_MASK)| \
SET(UART_C2_TE_MASK)|
SET(UART_C2_RE_MASK)| \
CLR(UART_C2_RWU_MASK)|
CLR(UART_C2_SBK_MASK), \
CLR(UART_S2_RXEDGIF_MASK)|
CLR(UART_S2_MSBF_MASK)| \
CLR(UART_S2_RXINV_MASK)|
CLR(UART_S2_RWUID_MASK)| \
CLR(UART_S2_BRK13_MASK), \
CLR(UART_C3_T8_MASK)|
CLR(UART_C3_TXDIR_MASK)| \
SET(UART_C3_TXINV_MASK)|
CLR(UART_C3_ORIE_MASK)| \
CLR(UART_C3_NEIE_MASK)|
CLR(UART_C3_FEIE_MASK)| \
CLR(UART_C3_PEIE_MASK), \
SET(UART_MA1_MA(0x00)), \
SET(UART_MA2_MA(0x00)), \
CLR(UART_C4_MAEN1_MASK)|
CLR(UART_C4_MAEN2_MASK)| \
CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
CLR(UART_C5_TDMAS_MASK)|
CLR(UART_C5_RDMAS_MASK) \
}
Configures UART to operate in interrupt mode. Receive data is not inverted. Transmit data is inverted.
- Parameters
-
brate | Baud rate. |
clk | Module clock in Hz:
UART0 | UART1 | UART2 | UART3 |
Bus clock | System clock | Bus clock | System clock |
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