MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
AFE Clocked by 8.0 MHz OSC, FEI Mode

This application demonstrates system oscillator clocked by 8.000 MHz External Crystal as the direct clocks source of the Analogue Front-End (AFE). The FLL is configured in FEI mode, clocked by internal 32 kHz low frequency oscillator, to generate 40 MHz core clock and 20.0 MHz Bus/Flash clock. The 4.0 MHz 50% duty-cycle sigma delta modulator clock, derived from 8.0 MHz External Crystal, is routed to pin PTB7 for monitoring purposes.

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* afequartz_test.c
******************************************************************************/
#include "drivers.h"
/* static data definitions */
static volatile int32 result;
void main (void)
{
/* enable clocks to all peripherals - clock mode 2:1:1 (core:bus:flash) */
/* route bus clock to PTF7 */
/* configures AFE_CLK pad to output mode and routes it to PTK4 */
/* system oscillator and FLL settings */
FLL_Init (FLL_MODULE_FEI_40_50MHZ_OSC_RANGE_02_EN_CONFIG);
/* VREF module must be initialized after SIM module */
VREFL_Trim( 3); /* VREFL trimmed to 0.400 V */
/* afe clocking directly from system oscillator */
/* trigger AFE operation by SW */
/* main loop */
while (1)
{
{
AFE_Read (CH0, &result);
}
}
}
Appconfig.h:
/******************************************************************************
* (c) Copyright 2010, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
***************************************************************************/
#ifndef __APPCONFIG_H
#define __APPCONFIG_H
/***************************************************************************/
//#define MTB_RAM_RESERVE
/***************************************************************************/
#define BOOT_NMI_DISABLE
/***************************************************************************/
/***************************************************************************/
#define FLL_MODULE_FEI_40_50MHZ_OSC_RANGE_02_EN_CONFIG \
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x00))| \
SET(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x02))|CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x01)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x04)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
/******************************************************************************/
#endif /* __APPCONFIG_ */
Toolchain support:
IAR EWARM 7.40.7KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0