MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
AFE Module Configuration Structures

Overview

This section describes default configuration structures for AFE module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define AFE_MODULE_RJFORMAT_CONFIG(src, div, freq)
 Selects normal mode of operation with right justified 2's complement 32-bit output data format. More...
 
#define AFE_MODULE_LJFORMAT_CONFIG(src, div, freq)
 Selects normal mode of operation with left justified 2's complement 32-bit output data format. More...
 
#define AFE_MODULE_LPM_RJFORMAT_CONFIG(src, div, freq)
 Selects low power mode of operation with right justified 2's complement 32-bit output data format. More...
 
#define AFE_MODULE_LPM_LJFORMAT_CONFIG(src, div, freq)
 Selects low power mode of operation with left justified 2's complement 32-bit output data format. More...
 

Macro Definition Documentation

#define AFE_MODULE_RJFORMAT_CONFIG (   src,
  div,
  freq 
)
Value:
(tAFE){ \
/* CR */ SET(AFE_CR_MSTR_EN_MASK)|CLR(AFE_CR_SOFT_TRG0_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG1_MASK)|CLR(AFE_CR_SOFT_TRG2_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG3_MASK)|CLR(AFE_CR_LPM_EN_MASK)| \
/* .. */ SET(AFE_CR_RST_B_MASK)|SET(AFE_CR_DLY_OK_MASK)| \
/* .. */ SET(AFE_CR_RESULT_FORMAT_MASK)| \
/* .. */ SET(AFE_CR_STRTUP_CNT((uint8)((freq/(1<<div))*20e-6))), \
/* CKR */ AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}

Selects normal mode of operation with right justified 2's complement 32-bit output data format.

Parameters
srcSelect one of the AFE Clock Sources.
divSelect one of the AFE Clock Dividers.
freqClock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field.
#define AFE_MODULE_LJFORMAT_CONFIG (   src,
  div,
  freq 
)
Value:
(tAFE){ \
/* CR */ SET(AFE_CR_MSTR_EN_MASK)|CLR(AFE_CR_SOFT_TRG0_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG1_MASK)|CLR(AFE_CR_SOFT_TRG2_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG3_MASK)|CLR(AFE_CR_LPM_EN_MASK)| \
/* .. */ SET(AFE_CR_RST_B_MASK)|SET(AFE_CR_DLY_OK_MASK)| \
/* .. */ CLR(AFE_CR_RESULT_FORMAT_MASK)| \
/* .. */ SET(AFE_CR_STRTUP_CNT((uint8)((freq/(1<<div))*20e-6))), \
/* CKR */ AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}

Selects normal mode of operation with left justified 2's complement 32-bit output data format.

Parameters
srcSelect one of the AFE Clock Sources.
divSelect one of the AFE Clock Dividers.
freqClock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field.
#define AFE_MODULE_LPM_RJFORMAT_CONFIG (   src,
  div,
  freq 
)
Value:
(tAFE){ \
/* CR */ SET(AFE_CR_MSTR_EN_MASK)|CLR(AFE_CR_SOFT_TRG0_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG1_MASK)|CLR(AFE_CR_SOFT_TRG2_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG3_MASK)|SET(AFE_CR_LPM_EN_MASK)| \
/* .. */ SET(AFE_CR_RST_B_MASK)|SET(AFE_CR_DLY_OK_MASK)| \
/* .. */ SET(AFE_CR_RESULT_FORMAT_MASK)| \
/* .. */ SET(AFE_CR_STRTUP_CNT((uint8)((freq/(1<<div))*20e-6))), \
/* CKR */ AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}

Selects low power mode of operation with right justified 2's complement 32-bit output data format.

Parameters
srcSelect one of the AFE Clock Sources.
divSelect one of the AFE Clock Dividers.
freqClock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field.
#define AFE_MODULE_LPM_LJFORMAT_CONFIG (   src,
  div,
  freq 
)
Value:
(tAFE){ \
/* CR */ SET(AFE_CR_MSTR_EN_MASK)|CLR(AFE_CR_SOFT_TRG0_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG1_MASK)|CLR(AFE_CR_SOFT_TRG2_MASK)| \
/* .. */ CLR(AFE_CR_SOFT_TRG3_MASK)|SET(AFE_CR_LPM_EN_MASK)| \
/* .. */ SET(AFE_CR_RST_B_MASK)|SET(AFE_CR_DLY_OK_MASK)| \
/* .. */ CLR(AFE_CR_RESULT_FORMAT_MASK)| \
/* .. */ SET(AFE_CR_STRTUP_CNT((uint8)((freq/(1<<div))*20e-6))), \
/* CKR */ AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}

Selects low power mode of operation with left justified 2's complement 32-bit output data format.

Parameters
srcSelect one of the AFE Clock Sources.
divSelect one of the AFE Clock Dividers.
freqClock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field.