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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes default configuration structures for FLL module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
Macros | |
#define | FLL_MODULE_FEI_20_25MHZ_CONFIG |
FLL Engaged Internal (DCO Range: 20-25 MHz). FLL clocked by 32 KHz Internal Reference Clock. More... | |
#define | FLL_MODULE_FEI_40_50MHZ_CONFIG |
FLL Engaged Internal (DCO Range: 40-50 MHz). FLL clocked by 32 KHz Internal Reference Clock. More... | |
#define | FLL_MODULE_FEI_60_75MHZ_CONFIG |
FLL Engaged Internal (DCO Range: 60-75 MHz). FLL clocked by 32 KHz Internal Reference Clock. More... | |
#define | FLL_MODULE_FEE_24MHZ_CONFIG |
FLL Engaged External (DCO Range: 24 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). More... | |
#define | FLL_MODULE_FEE_48MHZ_CONFIG |
FLL Engaged External (DCO Range: 48 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). More... | |
#define | FLL_MODULE_FEE_72MHZ_CONFIG |
FLL Engaged External (DCO Range: 72 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). More... | |
#define | FLL_MODULE_FBI_32KHZ_CONFIG |
FLL Bypassed Internal (32KHz). Clocked by Slow Internal Reference Clock. More... | |
#define | FLL_MODULE_FBI_2MHZ_CONFIG |
FLL Bypassed Internal (2MHz). Clocked by Fast Internal Reference Clock. More... | |
#define | FLL_MODULE_FBI_4MHZ_CONFIG |
FLL Bypassed Internal (4MHz). Clocked by Fast Internal Reference Clock. More... | |
#define | FLL_MODULE_FBE_OSC32K_CONFIG |
FLL Bypassed External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator. More... | |
#define | FLL_MODULE_FBE_8MHZ_OSC_CONFIG |
FLL Bypassed External (8.0MHz Crystal). Clocked by System Oscillator External Reference Clock. More... | |
#define | FLL_MODULE_BLPI_32KHZ_CONFIG |
FLL Bypassed Low Power Internal (32KHz). Clocked by Slow Internal Reference Clock. More... | |
#define | FLL_MODULE_BLPI_2MHZ_CONFIG |
FLL Bypassed Low Power Internal (2MHz). Clocked by Fast Internal Reference Clock. More... | |
#define | FLL_MODULE_BLPI_4MHZ_CONFIG |
FLL Bypassed Low Power Internal (4MHz). Clocked by Fast Internal Reference Clock. More... | |
#define | FLL_MODULE_BLPE_OSC32K_CONFIG |
FLL Bypassed Low Power External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator. More... | |
#define | FLL_MODULE_BLPE_OSC_CONFIG |
FLL Bypassed Low Power External. Clocked by System Oscillator External Reference Clock with Frequency Range 1.0 - 50 MHz. More... | |
#define | FLL_MODULE_FEE_20_25MHZ_DIV256_OSC_CONFIG |
FLL Engaged External (DCO Range: 20 - 25 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. More... | |
#define | FLL_MODULE_FEE_40_50MHZ_DIV256_OSC_CONFIG |
FLL Engaged External (DCO Range: 40 - 50 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. More... | |
#define | FLL_MODULE_FEE_60_75MHZ_DIV256_OSC_CONFIG |
FLL Engaged External (DCO Range: 60 - 75 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. More... | |
#define FLL_MODULE_FEI_20_25MHZ_CONFIG |
#define FLL_MODULE_FEI_40_50MHZ_CONFIG |
#define FLL_MODULE_FEI_60_75MHZ_CONFIG |
FLL Engaged Internal (DCO Range: 60-75 MHz). FLL clocked by 32 KHz Internal Reference Clock. Use SIM_SetClkDiv and SIM_SetClkMode to divide core and bus clocks to allowed ranges.
#define FLL_MODULE_FEE_24MHZ_CONFIG |
#define FLL_MODULE_FEE_48MHZ_CONFIG |
#define FLL_MODULE_FEE_72MHZ_CONFIG |
FLL Engaged External (DCO Range: 72 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). Use SIM_SetClkDiv and SIM_SetClkMode to divide core and bus clocks to allowed ranges.
#define FLL_MODULE_FBI_32KHZ_CONFIG |
#define FLL_MODULE_FBI_2MHZ_CONFIG |
#define FLL_MODULE_FBI_4MHZ_CONFIG |
#define FLL_MODULE_FBE_OSC32K_CONFIG |
#define FLL_MODULE_FBE_8MHZ_OSC_CONFIG |
#define FLL_MODULE_BLPI_32KHZ_CONFIG |
#define FLL_MODULE_BLPI_2MHZ_CONFIG |
#define FLL_MODULE_BLPI_4MHZ_CONFIG |
#define FLL_MODULE_BLPE_OSC32K_CONFIG |
#define FLL_MODULE_BLPE_OSC_CONFIG |
#define FLL_MODULE_FEE_20_25MHZ_DIV256_OSC_CONFIG |
#define FLL_MODULE_FEE_40_50MHZ_DIV256_OSC_CONFIG |
#define FLL_MODULE_FEE_60_75MHZ_DIV256_OSC_CONFIG |
FLL Engaged External (DCO Range: 60 - 75 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. Use SIM_SetClkDiv and SIM_SetClkMode to divide core and bus clocks to allowed ranges.