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MKMxxZxxACxx5 Bare Metal Software Drivers
R4.1.6
Reference Manual
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List of peripheral slots.
Macros | |
#define | AIPS_AIPS_SLOT |
Slot 0: Peripheral Bridge (AIPS Lite) | |
#define | AIPS_DMA_SLOT |
Slot 8: DMA Controller Module (DMA) | |
#define | AIPS_MPU_SLOT |
Slot 10: Memory Protection Unit (MPU) | |
#define | AIPS_FLASH_SLOT |
Slot 32: Flash Registers (FTFA) | |
#define | AIPS_DMUX0_SLOT |
Slot 33: DMA Memory Access Multiplexer 0 (DMAMUX0) | |
#define | AIPS_DMUX1_SLOT |
Slot 34: DMA Memory Access Multiplexer 1 (DMAMUX1) | |
#define | AIPS_DMUX2_SLOT |
Slot 35: DMA Memory Access Multiplexer 2 (DMAMUX2) | |
#define | AIPS_DMUX3_SLOT |
Slot 36: DMA Memory Access Multiplexer 3 (DMAMUX3) | |
#define | AIPS_RNGA_SLOT |
Slot 41: Random Number Generator Accelerator (RNGA) | |
#define | AIPS_ADC_SLOT |
Slot 43: SAR Analog-to-Digital Converter (ADC) | |
#define | AIPS_PIT0_SLOT |
Slot 45: Periodic Interrupt Timer 0 (PIT0) | |
#define | AIPS_PIT1_SLOT |
Slot 46: Periodic Interrupt Timer 1 (PIT1) | |
#define | AIPS_AFE_SLOT |
Slot 48: Analog Front End (AFE) | |
#define | AIPS_CRC_SLOT |
Slot 52: Programmable CRC (CRC) | |
#define | AIPS_LPTMR_SLOT |
Slot 60: Low Power Timer (LPTMR) | |
#define | AIPS_SIMLP_SLOT |
Slot 62: SIM Low Power Logic (SIMLP) | |
#define | AIPS_SIMHP_SLOT |
Slot 63: SIM High Power Logic (SIMHP) | |
#define | AIPS_SLCD_SLOT |
Slot 67: Segment LCD (SLCD) | |
#define | AIPS_PORTA_SLOT |
Slot 70: Port A Pin Mux Control (PORTA) | |
#define | AIPS_PORTB_SLOT |
Slot 71: Port B Pin Mux Control (PORTB) | |
#define | AIPS_PORTC_SLOT |
Slot 72: Port C Pin Mux Control (PORTC) | |
#define | AIPS_PORTD_SLOT |
Slot 73: Port D Pin Mux Control (PORTD) | |
#define | AIPS_PORTE_SLOT |
Slot 74: Port E Pin Mux Control (PORTE) | |
#define | AIPS_PORTF_SLOT |
Slot 75: Port F Pin Mux Control (PORTF) | |
#define | AIPS_PORTG_SLOT |
Slot 76: Port G Pin Mux Control (PORTG) | |
#define | AIPS_PORTH_SLOT |
Slot 77: Port H Pin Mux Control (PORTH) | |
#define | AIPS_PORTI_SLOT |
Slot 78: Port I Pin Mux Control (PORTI) | |
#define | AIPS_IRTC_SLOT |
Slot 80: Independent Real Time Clock (IRTC) | |
#define | AIPS_IRTCRAM_SLOT |
Slot 81: IRTC's 32 Byte Standby RAM (IRTCRAM) | |
#define | AIPS_WDOG_SLOT |
Slot 83: Watchdog Timer (WDOG) | |
#define | AIPS_XBAR_SLOT |
Slot 85: Peripheral Crossbar (XBAR) | |
#define | AIPS_TMR0_SLOT |
Slot 87: Quad Timer Channel 0 (TMR0) | |
#define | AIPS_TMR1_SLOT |
Slot 88: Quad Timer Channel 1 (TMR1) | |
#define | AIPS_TMR2_SLOT |
Slot 89: Quad Timer Channel 2 (TMR2) | |
#define | AIPS_TMR3_SLOT |
Slot 90: Quad Timer Channel 3 (TMR3) | |
#define | AIPS_EWM_SLOT |
Slot 97: External Watchdog Monitor (EWM) | |
#define | AIPS_MCG_SLOT |
Slot 100: Multipurpose Clock Generator (MCG) | |
#define | AIPS_OSC_SLOT |
Slot 102: Oscillator (OSC) | |
#define | AIPS_I2C0_SLOT |
Slot 103: Inter-Integrated Circuit 0 (I2C0) | |
#define | AIPS_I2C1_SLOT |
Slot 104: Inter-Integrated Circuit 1 (I2C1) | |
#define | AIPS_UART0_SLOT |
Slot 106: Universal Asynchronous Receiver/Transmitter 0 (UART0) | |
#define | AIPS_UART1_SLOT |
Slot 107: Universal Asynchronous Receiver/Transmitter 1 (UART1) | |
#define | AIPS_UART2_SLOT |
Slot 108: Universal Asynchronous Receiver/Transmitter 2 (UART2) | |
#define | AIPS_UART3_SLOT |
Slot 109: Universal Asynchronous Receiver/Transmitter 3 (UART3) | |
#define | AIPS_VREF_SLOT |
Slot 111: Voltage Reference (VREF) | |
#define | AIPS_CMP_SLOT |
Slot 114: Comparator (CMP) | |
#define | AIPS_SPI0_SLOT |
Slot 117: Serial Peripheral Interface 0 (SPI0) | |
#define | AIPS_SPI1_SLOT |
Slot 118: Serial Peripheral Interface 1 (SPI1) | |
#define | AIPS_RCM_SLOT |
Slot 123: Reset Control Module (RCM) | |
#define | AIPS_LLWU_SLOT |
Slot 124: Low Leakage Wakeup Unit (LLWU) | |
#define | AIPS_PMC_SLOT |
Slot 125: Power Management Controller (PMC) | |
#define | AIPS_SMC_SLOT |
Slot 126: System Mode Controller (SMC) | |
#define | AIPS_ALL_SLOTS |
Selects all slots. | |