MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
GPIO Control Performance

This benchmark application demonstrates performance of the Peripheral Bridge (AIPS-Lite) and IOPORT, a special single-cycle interface with the ARM Cortex-M0+ core, for GPIO pin control. The code sets and clears PTF1 and PTF2 through the AIPS-Lite and IOPORT, respectively. The following figure shows timing of the GPIO pin control for non-optimized code - green waveform represents PTF1 and yellow waveform PTF2 pins.

iohw_noopt.jpg

The following figure shows timings of the GPIO pin toggling for code optimized for speed - green waveform represents PTF1 and yellow waveform PTF2 pins.

iohw_speed.jpg

GPIO pin control timings for 2 MHz core and bus clocks executed in a while(1){..} loop for non-optimized and optimized codes are summarized below:

Performance AIPS (Lite)IOPORT
Toggle time; opt = none2.975us 2.016us
Toggle time; opt = speed1.504us 0.448us
Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* ioport_test.c
******************************************************************************/
#include "drivers.h"
void main (void)
{
/* SYSCLK:BUSCLK:FLASHCLK = 1:1:1 */
while(1)
{
/* PTF1 pin controlled via Peripheral Bridge (AIPS-Lite) */
GPIO_Set (GPIOF , PIN1);
GPIO_Clr (GPIOF , PIN1);
/* PTF2 pin controlled via IOPORT */
GPIO_Set (FGPIOF, PIN2);
GPIO_Clr (FGPIOF, PIN2);
}
}
Summary:
The GPIO control benchmark application demonstrated that accesses accelerated via Peripheral Bridge (AIPS-Lite) is slower in comparison with IOPORT accesses.