This section describes functions and macros of the driver's API.
#define FLL_SetSlowClkTrimVal |
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This macro sets slow clock trim value (SCTRIM and SCFTRIM bits). Increasing the trim value increases the period, and decreasing the value decreases the period. Upon reset this value is loaded with a factory trim value.
- Parameters
-
x | 9-bit trim value in range from 0 to 511. |
- Note
- Implemented as an inline macro.
- See also
- FLL_GetSlowClkTrimVal
#define FLL_GetSlowClkTrimVal |
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This macro returns slow clock trim value (SCTRIM and SCFTRIM bits).
- Returns
- 9-bit trim value in range from 0 to 511.
- Note
- Implemented as an inline macro.
- See also
- FLL_SetSlowClkTrimVal
#define FLL_SetFastClkTrimVal |
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This macro sets slow fast clock trim value (FCTRIM bits). Increasing the trim value increases the period, and decreasing the value decreases the period. Upon reset this value is loaded with a factory trim value.
- Parameters
-
x | 4-bit trim value in range from 0 to 15. |
- Note
- Implemented as an inline macro.
- See also
- FLL_GetFastClkTrimVal
#define FLL_GetFastClkTrimVal |
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This macro returns fast clock trim value (FCTRIM bits).
- Returns
- 4-bit trim value in range from 0 to 15.
- Note
- Implemented as an inline macro.
- See also
- FLL_SetFastClkTrimVal
#define FLL_SetFastClkDiv |
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This macros select fast clock internal reference divider (FCRDIV).
- Parameters
-
- Note
- Implemented as an inline macro.
- Warning
- Fast clock internal reference divider must be selected before fast IRC is enabled.
#define FLL_SetExtRefDiv |
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This macro select FLL's external reference divider (FRDIV) and frequency range select (RANGE0).
- Parameters
-
- Note
- Implemented as an inline macro.
- Warning
- Fast clock internal reference divider must be selected before fast IRC is enabled.
#define FLL_CtrlIRCLKEN |
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This macro enables/disables internal reference clock for use as MCGIRCLK.
- Parameters
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x | TRUE (MCGIRCLK active)
FALSE (MCGIRCLK inactive). |
- Note
- Implemented as an inline macro.
- See also
- FLL_CtrlIREFSTEN
#define FLL_CtrlIREFSTEN |
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This macro enables/disables internal reference clock activity when the MCG enters Stop mode.
- Parameters
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x | TRUE (Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode), FALSE (Internal reference clock is disabled in Stop mode). |
- Note
- Implemented as an inline macro.
- See also
- FLL_CtrlIRCLKEN
This macro enables/disables FLL activity in BLPI and BLPE modes.
- Parameters
-
x | TRUE (FLL is disabled in bypass modes), FALSE (FLL is enabled in bypass modes). |
- Note
- Implemented as an inline macro.
- Warning
- In FBE or PBE modes, calling setting LP bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect.
This macros Enables/disables external clock monitor.
- Parameters
-
x | TRUE (External clock monitor is disabled and generate a reset request on loss of external clock), FALSE (External clock monitor is disabled). |
- Note
- Implemented as an inline macro.
- Warning
- The CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled. Whenever the CME bit is set to a logic 1, the value of the RANGE bits in the C2 register should not be changed. CME bit should be set to a logic 0 before the MCG enters Stop mode. Otherwise, a reset request may occur while in Stop mode. CME should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
#define FLL_SelIRCSCLK |
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This macro selects IRCSCLK clock source.
- Parameters
-
- Note
- Implemented as an inline macro.
This function initializes Frequency-locked Loop (FLL).
- Parameters
-
- Note
- Implemented as a function call.
- See also
- PLL_Init