This section describes default configuration structures for IRTC module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define IRTC_MODULE_COMP_OFF_CONFIG |
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lfsr_clk, |
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lfsr_dur |
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Value:(tIRTC){ \
CLR(RTC_CTRL_SWR_MASK)|
CLR(RTC_CTRL_DST_EN_MASK)| \
CLR(RTC_CTRL_TIMER_STB_MASK_MASK)| \
SET(RTC_CTRL_ALM_MATCH(0x00))| \
CLR(RTC_CTRL_COMP_EN_MASK)|
CLR(RTC_CTRL_FINEEN_MASK), \
SET(RTC_COMPEN_COMPEN_VAL(0x0)), \
SET(RTC_TAMPER_QSCR_LFSR_DURATION(lfsr_dur))| \
SET(RTC_TAMPER_QSCR_LFSR_CLK_SEL(lfsr_clk))| \
CLR(RTC_TAMPER_QSCR_Q_CLEAR_MASK)| \
CLR(RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) \
}
Configuration options:
- Software Reset not performed
- Daylight Saving disabled (daylight saving registers preset by 0)
- Sampling clocks are not gated when in standby mode
- Only Seconds, Minutes, and Hours matched to generate an alarm
- Compensation disabled (coarse compensation type preselected)
- Queue full interrupt disabled
- Parameters
-
#define IRTC_MODULE_COMP_COARSE_CONFIG |
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lfsr_clk, |
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lfsr_dur, |
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interval, |
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value |
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Value:(tIRTC){ \
CLR(RTC_CTRL_SWR_MASK)|
CLR(RTC_CTRL_DST_EN_MASK)| \
CLR(RTC_CTRL_TIMER_STB_MASK_MASK)| \
SET(RTC_CTRL_ALM_MATCH(0x00))| \
SET(RTC_CTRL_COMP_EN_MASK)|
CLR(RTC_CTRL_FINEEN_MASK), \
SET(RTC_COMPEN_COMPEN_VAL((interval<<8)|value)), \
SET(RTC_TAMPER_QSCR_LFSR_DURATION(lfsr_dur))| \
SET(RTC_TAMPER_QSCR_LFSR_CLK_SEL(lfsr_clk))| \
CLR(RTC_TAMPER_QSCR_Q_CLEAR_MASK)| \
CLR(RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) \
}
Configuration options:
- Software Reset not performed
- Daylight Saving disabled (daylight saving registers preset by 0)
- Sampling clocks are not gated when in standby mode
- Only Seconds, Minutes, and Hours matched to generate an alarm
- Coarse compensation enabled
- Queue full interrupt disabled
- Parameters
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lfsr_clk | Clock selection for LFSR module IRTC Line Following Shift Register Clocks. |
lfsr_dur | LFSR Filter duration period from 0 to 15. |
interval | Compensation Interval is the duration in seconds over which the correction is applied. This is the time in which the addition or removal of 32.768 KHz clock cycles is done thereby ensuring that the compensation interval is close to the interval obtained with an ideal 1 Hz clock. Range of Compensation Interval: 1 second to 255 seconds. |
value | Compensation/Correction Value is a 2's complement format by which the 1 Hz Clock is modified by either adding or removing RTC Oscillator clock cycles. Range of Compensation: -128 to +127 (32.768 KHz clock cycles). |
#define IRTC_MODULE_COMP_FINE_CONFIG |
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lfsr_clk, |
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lfsr_dur, |
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integer, |
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fraction |
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Value:(tIRTC){ \
CLR(RTC_CTRL_SWR_MASK)|
CLR(RTC_CTRL_DST_EN_MASK)| \
CLR(RTC_CTRL_TIMER_STB_MASK_MASK)| \
SET(RTC_CTRL_ALM_MATCH(0x00))| \
SET(RTC_CTRL_COMP_EN_MASK)|
SET(RTC_CTRL_FINEEN_MASK), \
SET(RTC_COMPEN_COMPEN_VAL((integer<<12)|fraction)), \
SET(RTC_TAMPER_QSCR_LFSR_DURATION(lfsr_dur))| \
SET(RTC_TAMPER_QSCR_LFSR_CLK_SEL(lfsr_clk))| \
CLR(RTC_TAMPER_QSCR_Q_CLEAR_MASK)| \
CLR(RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) \
}
Configuration options:
- Software Reset not performed
- Daylight Saving disabled (daylight saving registers preset by 0)
- Sampling clocks are not gated when in standby mode
- Only Seconds, Minutes, and Hours matched to generate an alarm
- Fine compensation enabled
- Queue full interrupt disabled
- Parameters
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lfsr_clk | Clock selection for LFSR module IRTC Line Following Shift Register Clocks. |
lfsr_dur | LFSR Filter duration period from 0 to 15. |
integer | Integral Compensation Value is a 2's complement value of the integer part of correction that has to be adjusted in every 1 second period. Range of Compensation: from -8 to +7 (32.768 KHz clock cycles). |
fraction | Fraction Compensation Value is the fractional part of the correction value that has to be adjusted. This value is expressed as number of clock cycles of a fixed 4.194304 MHz clock. Range of Compensation Interval: from 0 (0us delay) to 127 (30.279us delay). |
- Warning
- The fine compensation requires MCGIRCLK to operate. You may enable this clock by calling FLL_CtrlIRCLKEN(TRUE) macro. Since the IRC clock is generated on MCU, this clock will get disabled when MCU power is OFF or in certain low power modes. In this case, the coarse 1 Hz clock is outputted from the MCU. The coarse 1 Hz clock is not a 50% duty cycle clock. You can also change MCGIRCLK clock frequency from 2.097152 MHz (default frequency) to 4.194304 MHz by calling FLL_SetFastClkDiv(FIRC_DIV1) macro.