This section describes default configuration structures for EWM module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define EWM_MODULE_IN_EN_CONFIG |
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clksrc, |
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presc, |
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per_lo, |
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per_hi |
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) |
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Value:(tEWM){ \
SET(EWM_CTRL_INTEN_MASK)|
SET(EWM_CTRL_INEN_MASK)| \
CLR(EWM_CTRL_ASSIN_MASK)|
SET(EWM_CTRL_EWMEN_MASK), \
per_lo, \
per_hi, \
clksrc, \
presc, \
}
The EWM input is enabled, no input assert inverted (default assert state is 0).
- Parameters
-
clksrc | Select one of the EWM Clock Sources. |
presc | Clock source prescaler (0-256), prescaled clock frequency is equal to frequency of the clksrc/(1+presc). The divided clock must be no more than half of the bus clock frequency. |
per_hi | Upper watchdog window timeout in number of clock cycles. |
per_lo | Lower watchdog window timeout in number of clock cycles. |
#define EWM_MODULE_IN_EN_INVERT_CONFIG |
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clksrc, |
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presc, |
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per_lo, |
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per_hi |
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) |
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Value:(tEWM){ \
SET(EWM_CTRL_INTEN_MASK)|
SET(EWM_CTRL_INEN_MASK)| \
SET(EWM_CTRL_ASSIN_MASK)|
SET(EWM_CTRL_EWMEN_MASK), \
per_lo, \
per_hi, \
clksrc, \
presc, \
}
The EWM input is enabled, input assert inversion (default assert state is 1).
- Parameters
-
clksrc | Select one of the EWM Clock Sources. |
presc | Clock source prescaler (0-256), prescaled clock frequency is equal to frequency of the clksrc/(1+presc). The divided clock must be no more than half of the bus clock frequency. |
per_hi | Upper watchdog window timeout in number of clock cycles. |
per_lo | Lower watchdog window timeout in number of clock cycles. |
#define EWM_MODULE_IN_DI_CONFIG |
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clksrc, |
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presc, |
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per_lo, |
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per_hi |
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) |
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Value:(tEWM){ \
SET(EWM_CTRL_INTEN_MASK)|
CLR(EWM_CTRL_INEN_MASK)| \
CLR(EWM_CTRL_ASSIN_MASK)|
SET(EWM_CTRL_EWMEN_MASK), \
per_lo, \
per_hi, \
clksrc, \
presc, \
}
The EWM input is disabled.
- Parameters
-
clksrc | Select one of the EWM Clock Sources. |
presc | Clock source prescaler (0-256), prescaled clock frequency is equal to frequency of the clksrc/(1+presc). The divided clock must be no more than half of the bus clock frequency. |
per_hi | Upper watchdog window timeout in number of clock cycles. |
per_lo | Lower watchdog window timeout in number of clock cycles. |