MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
MMAU Interrupt Configurations

Overview

This section describes several configurations of the MMAU that user may chose to generate interrupts.

Macros

#define MMAU_DZIE_DI_VIE_DI_QIE_DI_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_EN_VIE_DI_QIE_DI_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_DI_VIE_EN_QIE_DI_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_EN_VIE_EN_QIE_DI_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_DI_VIE_DI_QIE_EN_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_EN_VIE_DI_QIE_EN_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_DI_VIE_EN_QIE_EN_CONFIG
 Disable all interrupts of the MMAU module. More...
 
#define MMAU_DZIE_EN_VIE_EN_QIE_EN_CONFIG
 Enable all interrupts of the MMAU module. More...
 

Macro Definition Documentation

#define MMAU_DZIE_DI_VIE_DI_QIE_DI_CONFIG
Value:
(tMMAU){ \
/* CR */ CLR(MMAU_CSR_DZIE_MASK)|CLR(MMAU_CSR_VIE_MASK)|CLR(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt disabled.
  • Divide/Multiply Overflow (V flag) Interrupt disabled.
  • Accumulation Overflow (Q flag) Interrupt disabled.
#define MMAU_DZIE_EN_VIE_DI_QIE_DI_CONFIG
Value:
(tMMAU){ \
/* CR */ SET(MMAU_CSR_DZIE_MASK)|CLR(MMAU_CSR_VIE_MASK)|CLR(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt enabled.
  • Divide/Multiply Overflow (V flag) Interrupt disabled.
  • Accumulation Overflow (Q flag) Interrupt disabled.
#define MMAU_DZIE_DI_VIE_EN_QIE_DI_CONFIG
Value:
(tMMAU){ \
/* CR */ CLR(MMAU_CSR_DZIE_MASK)|SET(MMAU_CSR_VIE_MASK)|CLR(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt disabled.
  • Divide/Multiply Overflow (V flag) Interrupt enabled.
  • Accumulation Overflow (Q flag) Interrupt disabled.
#define MMAU_DZIE_EN_VIE_EN_QIE_DI_CONFIG
Value:
(tMMAU){ \
/* CR */ SET(MMAU_CSR_DZIE_MASK)|SET(MMAU_CSR_VIE_MASK)|CLR(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt enabled.
  • Divide/Multiply Overflow (V flag) Interrupt enabled.
  • Accumulation Overflow (Q flag) Interrupt disabled.
#define MMAU_DZIE_DI_VIE_DI_QIE_EN_CONFIG
Value:
(tMMAU){ \
/* CR */ CLR(MMAU_CSR_DZIE_MASK)|CLR(MMAU_CSR_VIE_MASK)|SET(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt disabled.
  • Divide/Multiply Overflow (V flag) Interrupt disabled.
  • Accumulation Overflow (Q flag) Interrupt enabled.
#define MMAU_DZIE_EN_VIE_DI_QIE_EN_CONFIG
Value:
(tMMAU){ \
/* CR */ SET(MMAU_CSR_DZIE_MASK)|CLR(MMAU_CSR_VIE_MASK)|SET(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt enabled.
  • Divide/Multiply Overflow (V flag) Interrupt disabled.
  • Accumulation Overflow (Q flag) Interrupt enabled.
#define MMAU_DZIE_DI_VIE_EN_QIE_EN_CONFIG
Value:
(tMMAU){ \
/* CR */ CLR(MMAU_CSR_DZIE_MASK)|SET(MMAU_CSR_VIE_MASK)|SET(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt disabled.
  • Divide/Multiply Overflow (V flag) Interrupt enabled.
  • Accumulation Overflow (Q flag) Interrupt enabled.
#define MMAU_DZIE_EN_VIE_EN_QIE_EN_CONFIG
Value:
(tMMAU){ \
/* CR */ SET(MMAU_CSR_DZIE_MASK)|SET(MMAU_CSR_VIE_MASK)|SET(MMAU_CSR_QIE_MASK) \
}

This configuration structure configures interrupts of the MMAU as follows:

  • Divide-by-Zero Interrupt enabled.
  • Divide/Multiply Overflow (V flag) Interrupt enabled.
  • Accumulation Overflow (Q flag) Interrupt enabled.