MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
SIM Configuration Structures

Overview

This section describes default configuration structures for SIM module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define SIM_MODULE_ALL_PERIPH_ON_CONFIG
 Full configuration. More...
 
#define SIM_MODULE_ALL_PERIPH_OFF_CONFIG
 Minimum configuration. More...
 

Macro Definition Documentation

#define SIM_MODULE_ALL_PERIPH_ON_CONFIG
Value:
(tSIM){ \
/* SOPT1 */ SET(SIM_SOPT1_OSC32KSEL(0)), \
/* SOPT1_CFG*/ CLR(SIM_SOPT1_CFG_RAMBPEN_MASK)|CLR(SIM_SOPT1_CFG_RAMSBDIS_MASK)|\
/* .........*/ SET(SIM_SOPT1_CFG_LPTMR3SEL(0))|SET(SIM_SOPT1_CFG_LPTMR2SEL(0))| \
/* .........*/ SET(SIM_SOPT1_CFG_LPTMR1SEL(0))|SET(SIM_SOPT1_CFG_LPTMR0SEL(0)), \
/* CTRL_REG */ CLR(SIM_CTRL_REG_TMRFREEZE_MASK)|SET(SIM_CTRL_REG_LPUARTSRC(1))| \
/* ........ */ CLR(SIM_CTRL_REG_AFEOUTCLKSEL_MASK)| \
/* ........ */ SET(SIM_CTRL_REG_XBARCLKOUT(0))|SET(SIM_CTRL_REG_PLLFLLSEL(2))| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV3_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV2_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV1_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV0_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV3_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV2_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV1_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV0_MASK)| \
/* ........ */ SET(SIM_CTRL_REG_CLKOUT(0))| \
/* ........ */ SET(SIM_CTRL_REG_ADCTRGSEL(0))| \
/* ........ */ CLR(SIM_CTRL_REG_PLLVLPEN_MASK)|SET(SIM_CTRL_REG_NMIDIS_MASK), \
/* SCGC4 */ SET(SIM_SCGC4_SPI1_MASK)|SET(SIM_SCGC4_SPI0_MASK)| \
/* ........ */ SET(SIM_SCGC4_CMP_MASK)|SET(SIM_SCGC4_VREF_MASK)| \
/* ........ */ SET(SIM_SCGC4_UART3_MASK)|SET(SIM_SCGC4_UART2_MASK)| \
/* ........ */ SET(SIM_SCGC4_UART1_MASK)|SET(SIM_SCGC4_UART0_MASK)| \
/* ........ */ SET(SIM_SCGC4_I2C1_MASK)|SET(SIM_SCGC4_I2C0_MASK)| \
/* ........ */ SET(SIM_SCGC4_EWM_MASK), \
/* SCGC5 */ SET(SIM_SCGC5_TMR3_MASK)|SET(SIM_SCGC5_TMR2_MASK)| \
/* ........ */ SET(SIM_SCGC5_TMR1_MASK)|SET(SIM_SCGC5_TMR0_MASK)| \
/* ........ */ SET(SIM_SCGC5_XBAR_MASK)|SET(SIM_SCGC5_RTCREG_MASK)| \
/* ........ */ SET(SIM_SCGC5_RTC_MASK)| \
/* ........ */ SET(SIM_SCGC5_PORTI_MASK)|SET(SIM_SCGC5_PORTH_MASK)| \
/* ........ */ SET(SIM_SCGC5_PORTG_MASK)|SET(SIM_SCGC5_PORTF_MASK)| \
/* ........ */ SET(SIM_SCGC5_PORTE_MASK)|SET(SIM_SCGC5_PORTD_MASK)| \
/* ........ */ SET(SIM_SCGC5_PORTC_MASK)|SET(SIM_SCGC5_PORTB_MASK)| \
/* ........ */ SET(SIM_SCGC5_PORTA_MASK)|SET(SIM_SCGC5_SLCD_MASK), \
/* SCGC6 */ SET(SIM_SCGC6_LPTMR_MASK)|SET(SIM_SCGC6_PORTM_MASK)| \
/* ........ */ SET(SIM_SCGC6_PORTL_MASK)|SET(SIM_SCGC6_PORTK_MASK)| \
/* ........ */ SET(SIM_SCGC6_PORTJ_MASK)|SET(SIM_SCGC6_PDB_MASK)| \
/* ........ */ SET(SIM_SCGC6_CRC_MASK)|SET(SIM_SCGC6_AFE_MASK)| \
/* ........ */ SET(SIM_SCGC6_PIT1_MASK)|SET(SIM_SCGC6_PIT0_MASK)| \
/* ........ */ SET(SIM_SCGC6_ADC_MASK)|SET(SIM_SCGC6_LPUART_MASK)| \
/* ........ */ SET(SIM_SCGC6_RNGA_MASK)|SET(SIM_SCGC6_DMACHMUX_MASK)| \
/* ........ */ SET(SIM_SCGC6_FTFA_MASK), \
/* SCGC7 */ SET(SIM_SCGC7_CAU_MASK)|SET(SIM_SCGC7_DMA_MASK)| \
/* ........ */ SET(SIM_SCGC7_MPU_MASK), \
/* CLKDIV1 */ SET(SIM_CLKDIV1_CLKDIVSYS(0))|SET(SIM_CLKDIV1_CLKDIVBUS(1))| \
/* ........ */ CLR(SIM_CLKDIV1_FLASHCLKMODE_MASK), \
/* FCFG1 */ CLR(SIM_FCFG1_FLASHDOZE_MASK)|CLR(SIM_FCFG1_FLASHDIS_MASK), \
/* MISC_CTL */ SET(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_RTCCLKSEL_MASK)| \
/* ........ */ SET(SIM_MISC_CTL_TMR3PCSSEL(0))|SET(SIM_MISC_CTL_TMR2PCSSEL(0))| \
/* ........ */ SET(SIM_MISC_CTL_TMR1PCSSEL(0))|SET(SIM_MISC_CTL_TMR0PCSSEL(0))| \
/* ........ */ CLR(SIM_MISC_CTL_TMR3SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR2SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR1SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR0SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR0PLLSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_EWMINSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART3IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART2IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART1IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART0IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UARTMODTYPE_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_AFECLKPADDIR_MASK)| \
/* ........ */ SET(SIM_MISC_CTL_AFECLKSEL(0))|SET(SIM_MISC_CTL_DMADONESEL(0))| \
/* ........ */ CLR(SIM_MISC_CTL_PDBADCTRG_MASK) \
}

Configures System Integration Module to operate with the following characteristics:

  • All peripherals and ports clocked.
  • SYSCLK:BUSCLK:FLASHCLK = 2:1:1 clock mode.
  • Selects 32 KHz clock source for LPTMR, CLKOUT, LCD, EWM and WDOG.
  • Bitline precharge of system SRAM disabled during VLPR and VLPW modes.
  • Source bias of System SRAM enabled during VLPR and VLPW modes.
  • LP Timer channel3 sourced from PTD5.
  • LP Timer channel2 sourced from PTD6.
  • LP Timer channel1 sourced from PTE4.
  • LP Timer channel1 sourced from CMP[0] output.
  • QTRM counters operate normally (not frozen).
  • BUSCLK is used as LPUART clock.
  • AFE output clock is divided by AFE clock prescaler.
  • XBAR clock out select disabled.
  • SPI1 signal outputs not inverted.
  • SPI0 signal outputs not inverted.
  • Clock out select disabled.
  • BUSCLK is used as SAR ADC Trigger clock.
  • PLL disabled in VLP mode.
  • NMI Disabled (enabled after POR)
  • Flash remains enabled during wait mode.
  • Flash is enabled.
  • Vref buffer power down (when enabled it drives SAR, DAC and output PAD)).
  • Internal reference selected as vref buffer input.
  • Vref buffer does not drive PAD.
  • RTC OSC_32K clock selected as the RTC clock source.
  • Bus Clock selected as Timer Channel3 Primary Count Source.
  • Bus Clock selected as Timer Channel2 Primary Count Source.
  • Bus Clock selected as Timer Channel1 Primary Count Source.
  • Bus Clock selected as Timer Channel0 Primary Count Source.
  • Pad PTE5 or PTD1 drives Timer Channel3 Secondary Count Source.
  • Pad PTF7 or PTF0 drives Timer Channel2 Secondary Count Source.
  • Pad PTG0 or PTC6 drives Timer Channel1 Secondary Count Source.
  • Pad PTF1 or PTD5 drives Timer Channel0 Secondary Count Source.
  • Bus Clock selected as source for the Timer CH0.
  • External watchdog monitor input sourced from PTL[3],PTE[2] or PTE[4].
  • IR modulation disabled on all UARTs.
  • TypeA (OR'ed) modulation selected for IRDA.
  • AFE CLK PAD is input.
  • AFE clocked from MCG PLL Clock Source.
  • DMA Done flag driven by DMA0.
  • PDB via XBAR to trigger ADC.
#define SIM_MODULE_ALL_PERIPH_OFF_CONFIG
Value:
(tSIM){ \
/* SOPT1 */ SET(SIM_SOPT1_OSC32KSEL(0)), \
/* SOPT1_CFG*/ CLR(SIM_SOPT1_CFG_RAMBPEN_MASK)|CLR(SIM_SOPT1_CFG_RAMSBDIS_MASK)|\
/* .........*/ SET(SIM_SOPT1_CFG_LPTMR3SEL(0))|SET(SIM_SOPT1_CFG_LPTMR2SEL(0))| \
/* .........*/ SET(SIM_SOPT1_CFG_LPTMR1SEL(0))|SET(SIM_SOPT1_CFG_LPTMR0SEL(0)), \
/* CTRL_REG */ CLR(SIM_CTRL_REG_TMRFREEZE_MASK)|SET(SIM_CTRL_REG_LPUARTSRC(1))| \
/* ........ */ CLR(SIM_CTRL_REG_AFEOUTCLKSEL_MASK)| \
/* ........ */ SET(SIM_CTRL_REG_XBARCLKOUT(0))|SET(SIM_CTRL_REG_PLLFLLSEL(2))| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV3_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV2_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV1_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI1_INV0_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV3_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV2_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV1_MASK)| \
/* ........ */ CLR(SIM_CTRL_REG_SPI0_INV0_MASK)| \
/* ........ */ SET(SIM_CTRL_REG_CLKOUT(0))| \
/* ........ */ SET(SIM_CTRL_REG_ADCTRGSEL(0))| \
/* ........ */ CLR(SIM_CTRL_REG_PLLVLPEN_MASK)|SET(SIM_CTRL_REG_NMIDIS_MASK), \
/* SCGC4 */ CLR(SIM_SCGC4_SPI1_MASK)|CLR(SIM_SCGC4_SPI0_MASK)| \
/* ........ */ CLR(SIM_SCGC4_CMP_MASK)|CLR(SIM_SCGC4_VREF_MASK)| \
/* ........ */ CLR(SIM_SCGC4_UART3_MASK)|CLR(SIM_SCGC4_UART2_MASK)| \
/* ........ */ CLR(SIM_SCGC4_UART1_MASK)|CLR(SIM_SCGC4_UART0_MASK)| \
/* ........ */ CLR(SIM_SCGC4_I2C1_MASK)|CLR(SIM_SCGC4_I2C0_MASK)| \
/* ........ */ CLR(SIM_SCGC4_EWM_MASK), \
/* SCGC5 */ CLR(SIM_SCGC5_TMR3_MASK)|CLR(SIM_SCGC5_TMR2_MASK)| \
/* ........ */ CLR(SIM_SCGC5_TMR1_MASK)|CLR(SIM_SCGC5_TMR0_MASK)| \
/* ........ */ CLR(SIM_SCGC5_XBAR_MASK)|CLR(SIM_SCGC5_RTCREG_MASK)| \
/* ........ */ CLR(SIM_SCGC5_RTC_MASK)| \
/* ........ */ CLR(SIM_SCGC5_PORTI_MASK)|CLR(SIM_SCGC5_PORTH_MASK)| \
/* ........ */ CLR(SIM_SCGC5_PORTG_MASK)|CLR(SIM_SCGC5_PORTF_MASK)| \
/* ........ */ CLR(SIM_SCGC5_PORTE_MASK)|CLR(SIM_SCGC5_PORTD_MASK)| \
/* ........ */ CLR(SIM_SCGC5_PORTC_MASK)|CLR(SIM_SCGC5_PORTB_MASK)| \
/* ........ */ CLR(SIM_SCGC5_PORTA_MASK)|CLR(SIM_SCGC5_SLCD_MASK), \
/* SCGC6 */ CLR(SIM_SCGC6_LPTMR_MASK)|CLR(SIM_SCGC6_PORTM_MASK)| \
/* ........ */ CLR(SIM_SCGC6_PORTL_MASK)|CLR(SIM_SCGC6_PORTK_MASK)| \
/* ........ */ CLR(SIM_SCGC6_PORTJ_MASK)|CLR(SIM_SCGC6_PDB_MASK)| \
/* ........ */ CLR(SIM_SCGC6_CRC_MASK)|CLR(SIM_SCGC6_AFE_MASK)| \
/* ........ */ CLR(SIM_SCGC6_PIT1_MASK)|CLR(SIM_SCGC6_PIT0_MASK)| \
/* ........ */ CLR(SIM_SCGC6_ADC_MASK)|CLR(SIM_SCGC6_LPUART_MASK)| \
/* ........ */ CLR(SIM_SCGC6_RNGA_MASK)|CLR(SIM_SCGC6_DMACHMUX_MASK)| \
/* ........ */ SET(SIM_SCGC6_FTFA_MASK), \
/* SCGC7 */ CLR(SIM_SCGC7_CAU_MASK)|CLR(SIM_SCGC7_DMA_MASK)| \
/* ........ */ CLR(SIM_SCGC7_MPU_MASK), \
/* CLKDIV1 */ SET(SIM_CLKDIV1_CLKDIVSYS(0))|SET(SIM_CLKDIV1_CLKDIVBUS(1))| \
/* ........ */ CLR(SIM_CLKDIV1_FLASHCLKMODE_MASK), \
/* FCFG1 */ CLR(SIM_FCFG1_FLASHDOZE_MASK)|CLR(SIM_FCFG1_FLASHDIS_MASK), \
/* MISC_CTL */ SET(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_RTCCLKSEL_MASK)| \
/* ........ */ SET(SIM_MISC_CTL_TMR3PCSSEL(0))|SET(SIM_MISC_CTL_TMR2PCSSEL(0))| \
/* ........ */ SET(SIM_MISC_CTL_TMR1PCSSEL(0))|SET(SIM_MISC_CTL_TMR0PCSSEL(0))| \
/* ........ */ CLR(SIM_MISC_CTL_TMR3SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR2SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR1SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR0SCSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_TMR0PLLSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_EWMINSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART3IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART2IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART1IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UART0IRSEL_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_UARTMODTYPE_MASK)| \
/* ........ */ CLR(SIM_MISC_CTL_AFECLKPADDIR_MASK)| \
/* ........ */ SET(SIM_MISC_CTL_AFECLKSEL(0))|SET(SIM_MISC_CTL_DMADONESEL(0))| \
/* ........ */ CLR(SIM_MISC_CTL_PDBADCTRG_MASK) \
}

Configures System Integration Module to operate with the following characteristics:

  • Only peripherals that are necessary for device operation are clocked.
  • SYSCLK:BUSCLK:FLASHCLK = 2:1:1 clock mode.
  • Selects 32 KHz clock source for LPTMR, CLKOUT, LCD, EWM and WDOG.
  • Bitline precharge of system SRAM disabled during VLPR and VLPW modes.
  • Source bias of System SRAM enabled during VLPR and VLPW modes.
  • LP Timer channel3 sourced from PTD5.
  • LP Timer channel2 sourced from PTD6.
  • LP Timer channel1 sourced from PTE4.
  • LP Timer channel1 sourced from CMP[0] output.
  • QTRM counters operate normally (not frozen).
  • BUSCLK is used as LPUART clock.
  • AFE output clock is divided by AFE clock prescaler.
  • XBAR clock out select disabled.
  • SPI1 signal outputs not inverted.
  • SPI0 signal outputs not inverted.
  • Clock out select disabled.
  • BUSCLK is used as SAR ADC Trigger clock.
  • PLL disabled in VLP mode.
  • NMI Disabled (enabled after POR).
  • Flash remains enabled during wait mode.
  • Flash is enabled.
  • Vref buffer powered down (when enabled it drives SAR, DAC and output PAD)).
  • Internal reference selected as vref buffer input.
  • Vref buffer does not drive PAD.
  • RTC OSC_32K clock selected as the RTC clock source.
  • Bus Clock selected as Timer Channel3 Primary Count Source.
  • Bus Clock selected as Timer Channel2 Primary Count Source.
  • Bus Clock selected as Timer Channel1 Primary Count Source.
  • Bus Clock selected as Timer Channel0 Primary Count Source.
  • Pad PTE5 or PTD1 drives Timer Channel3 Secondary Count Source.
  • Pad PTF7 or PTF0 drives Timer Channel2 Secondary Count Source.
  • Pad PTG0 or PTC6 drives Timer Channel1 Secondary Count Source.
  • Pad PTF1 or PTD5 drives Timer Channel0 Secondary Count Source.
  • Bus Clock selected as source for the Timer CH0.
  • External watchdog monitor input sourced from PTL[3],PTE[2] or PTE[4].
  • IR modulation disabled on all UARTs.
  • TypeA (OR'ed) modulation selected for IRDA.
  • AFE CLK PAD is input.
  • AFE clocked from MCG PLL Clock Source.
  • DMA Done flag driven by DMA0.
  • PDB via XBAR to trigger ADC.