MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
PDB Pulse Out Generation

This example shows typical use of the Programmable Delay Block (PDB) Pulse output function in software trigger mode. The PDB module is initially clocked with a BUSCLK. The BUSCLK is 1MHz in this case. PDB counter modulo is configured on 60000 count (after about 60ms the counter overflows). The delay 1 value is 0, so the rising edge occurs when the PDB counter has value 0. The delay 2 is configured on 10000 value (about 10ms), so the falling edge occurs when the PDB counter reaches value 10000. Pulse output signal (XBAR_IN51) is routed on the PL2 pin (XBAR_OUT10).

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* pdbpulse_test.c
******************************************************************************/
#include "drivers.h"
void main (void)
{
/* enable clocks to all on chip peripherals */
/* Route the PDB_Out signal to the PL2 pin where can be monitored. */
0,
NULL);
/* Initiate the PDB module with pulse output function */
/*Trigger the PDB counter */
while(1);
}
Toolchain support:
IAR EWARM 7.40.7KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0