MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
FLL Configuration Structures

Overview

This section describes default configuration structures for FLL module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define FLL_MODULE_FEI_20_25MHZ_CONFIG
 FLL Engaged Internal (DCO Range: 20-25 MHz). FLL clocked by 32 KHz Internal Reference Clock. More...
 
#define FLL_MODULE_FEI_40_50MHZ_CONFIG
 FLL Engaged Internal (DCO Range: 40-50 MHz). FLL clocked by 32 KHz Internal Reference Clock. More...
 
#define FLL_MODULE_FEE_24MHZ_CONFIG
 FLL Engaged External (DCO Range: 24 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). More...
 
#define FLL_MODULE_FEE_48MHZ_CONFIG
 FLL Engaged External (DCO Range: 48 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal). More...
 
#define FLL_MODULE_FBI_32KHZ_CONFIG
 FLL Bypassed Internal (32KHz). Clocked by Slow Internal Reference Clock. More...
 
#define FLL_MODULE_FBI_2MHZ_CONFIG
 FLL Bypassed Internal (2MHz). Clocked by Fast Internal Reference Clock. More...
 
#define FLL_MODULE_FBI_4MHZ_CONFIG
 FLL Bypassed Internal (4MHz). Clocked by Fast Internal Reference Clock. More...
 
#define FLL_MODULE_FBE_OSC32K_CONFIG
 FLL Bypassed External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator. More...
 
#define FLL_MODULE_FBE_8MHZ_OSC_CONFIG
 FLL Bypassed External (8.0MHz Crystal). Clocked by System Oscillator External Reference Clock. More...
 
#define FLL_MODULE_BLPI_32KHZ_CONFIG
 FLL Bypassed Low Power Internal (32KHz). Clocked by Slow Internal Reference Clock. More...
 
#define FLL_MODULE_BLPI_2MHZ_CONFIG
 FLL Bypassed Low Power Internal (2MHz). Clocked by Fast Internal Reference Clock. More...
 
#define FLL_MODULE_BLPI_4MHZ_CONFIG
 FLL Bypassed Low Power Internal (4MHz). Clocked by Fast Internal Reference Clock. More...
 
#define FLL_MODULE_BLPE_OSC32K_CONFIG
 FLL Bypassed Low Power External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator. More...
 
#define FLL_MODULE_BLPE_OSC_CONFIG
 FLL Bypassed Low Power External. Clocked by System Oscillator External Reference Clock with Frequency Range 1.0 - 50 MHz. More...
 
#define FLL_MODULE_FEE_20_25MHZ_DIV256_OSC_CONFIG
 FLL Engaged External (DCO Range: 20 - 25 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. More...
 
#define FLL_MODULE_FEE_40_50MHZ_DIV256_OSC_CONFIG
 FLL Engaged External (DCO Range: 40 - 50 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz. More...
 

Macro Definition Documentation

#define FLL_MODULE_FEI_20_25MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged Internal (DCO Range: 20-25 MHz). FLL clocked by 32 KHz Internal Reference Clock.

#define FLL_MODULE_FEI_40_50MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x01)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged Internal (DCO Range: 40-50 MHz). FLL clocked by 32 KHz Internal Reference Clock.

#define FLL_MODULE_FEE_24MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ SET(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|SET(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged External (DCO Range: 24 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal).

#define FLL_MODULE_FEE_48MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ SET(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x01)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|SET(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged External (DCO Range: 48 MHz). FLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal).

#define FLL_MODULE_FBI_32KHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Internal (32KHz). Clocked by Slow Internal Reference Clock.

#define FLL_MODULE_FBI_2MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Internal (2MHz). Clocked by Fast Internal Reference Clock.

#define FLL_MODULE_FBI_4MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x00)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Internal (4MHz). Clocked by Fast Internal Reference Clock.

#define FLL_MODULE_FBE_OSC32K_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x02))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|SET(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator.

#define FLL_MODULE_FBE_8MHZ_OSC_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x02))|SET(MCG_C1_FRDIV(0x03))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x02))|SET(MCG_C2_HGO0_MASK)|\
/* .. */ SET(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed External (8.0MHz Crystal). Clocked by System Oscillator External Reference Clock.

#define FLL_MODULE_BLPI_32KHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|SET(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Low Power Internal (32KHz). Clocked by Slow Internal Reference Clock.

#define FLL_MODULE_BLPI_2MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|SET(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Low Power Internal (2MHz). Clocked by Fast Internal Reference Clock.

#define FLL_MODULE_BLPI_4MHZ_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x01))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ SET(MCG_C1_IREFS_MASK)|SET(MCG_C1_IRCLKEN_MASK)| \
/* .. */ SET(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|SET(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x00)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Low Power Internal (4MHz). Clocked by Fast Internal Reference Clock.

#define FLL_MODULE_BLPE_OSC32K_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x02))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x00))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ CLR(MCG_C2_EREFS0_MASK)|SET(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|SET(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Low Power External (32.768KHz). Clocked by Slow External Reference Clock from OSC32K Oscillator.

#define FLL_MODULE_BLPE_OSC_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x02))|SET(MCG_C1_FRDIV(0x00))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x02))|CLR(MCG_C2_HGO0_MASK)|\
/* .. */ SET(MCG_C2_EREFS0_MASK)|SET(MCG_C2_LP_MASK)|CLR(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Bypassed Low Power External. Clocked by System Oscillator External Reference Clock with Frequency Range 1.0 - 50 MHz.

#define FLL_MODULE_FEE_20_25MHZ_DIV256_OSC_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x03))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x02))|SET(MCG_C2_HGO0_MASK)|\
/* .. */ SET(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x00)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged External (DCO Range: 20 - 25 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz.

#define FLL_MODULE_FEE_40_50MHZ_DIV256_OSC_CONFIG
Value:
(tFLL){ \
/* C1 */ SET(MCG_C1_CLKS(0x00))|SET(MCG_C1_FRDIV(0x03))| \
/* .. */ CLR(MCG_C1_IREFS_MASK)|CLR(MCG_C1_IRCLKEN_MASK)| \
/* .. */ CLR(MCG_C1_IREFSTEN_MASK), \
/* C2 */ SET(MCG_C2_LOCRE0_MASK)|SET(MCG_C2_RANGE0(0x02))|SET(MCG_C2_HGO0_MASK)|\
/* .. */ SET(MCG_C2_EREFS0_MASK)|CLR(MCG_C2_LP_MASK)|SET(MCG_C2_IRCS_MASK), \
/* C4 */ CLR(MCG_C4_DMX32_MASK)|SET(MCG_C4_DRST_DRS(0x01)), \
/* C6 */ CLR(MCG_C6_LOLIE0_MASK)|CLR(MCG_C6_PLLS_MASK)|CLR(MCG_C6_CME0_MASK)| \
/* .. */ SET(MCG_C6_CHGPMP_BIAS(0x08)), \
/* SC */ CLR(MCG_SC_ATME_MASK)|CLR(MCG_SC_ATMS_MASK)| \
/* .. */ CLR(MCG_SC_FLTPRSRV_MASK)|SET(MCG_SC_FCRDIV(0x01)), \
/* C7 */ SET(MCG_C7_PLL32KREFSEL(0))|CLR(MCG_C7_OSCSEL_MASK), \
/* C8 */ SET(MCG_C8_LOCRE1_MASK)|CLR(MCG_C8_LOLRE_MASK)|CLR(MCG_C8_CME1_MASK)|\
/* .. */ CLR(MCG_C8_COARSE_LOLIE_MASK), \
}

FLL Engaged External (DCO Range: 40 - 50 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz.