MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
PLL Engaged Controlled by 8.0 MHz OSC

This example shows PLL Engaged External (PEE) mode clocked by 8.0 MHz System Oscillator (OSC).

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* pllpeeosc_test.c
******************************************************************************/
#include "drivers.h"
void main (void)
{
/* enable clocks to all on chip peripherals */
/* route core clock to PTF7 for monitoring */
/* PLL settings */
while(1);
}
Toolchain support:
IAR EWARM 7.40.7CodeWarrior 10.6KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0