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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This example shows typical use of the Programmable Delay Block (PDB) Pulse output function in software trigger mode. The PDB module is initially clocked with a BUSCLK. The BUSCLK is 1MHz in this case. PDB counter modulo is configured on 60000 count (after about 60ms the counter overflows). The delay 1 value is 0, so the rising edge occurs when the PDB counter has value 0. The delay 2 is configured on 10000 value (about 10ms), so the falling edge occurs when the PDB counter reaches value 10000. Pulse output signal (XBAR_IN51) is routed on the PL2 pin (XBAR_OUT10).
IAR EWARM 7.40.7 | KEIL uVision 5.15 | CrossWorks 3.6 | ATOLLIC TrueStudio 5.3.0 | Kinetis Design Studio 3.0.0 |
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