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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes default configuration structures for ADC channel (result & status and control register). The 16-bit SAR ADC module on MKM34Z256VLx7 devices contains 4 result registers.
Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
Macros | |
#define | ADC_CH_SE_IRQ_CONFIG(ch) |
Single ended conversion, interrupt enabled. More... | |
#define | ADC_CH_SE_POLL_CONFIG(ch) |
Single ended conversion, polling mode (interrupt disabled). More... | |
#define | ADC_CH_DISABLE_CONFIG |
ADC module is disabled. More... | |
#define ADC_CH_SE_IRQ_CONFIG | ( | ch | ) |
Single ended conversion, interrupt enabled.
ch | Select one of the ADC Input Channels (MUXA) or ADC Input Channels (MUXB). |
#define ADC_CH_SE_POLL_CONFIG | ( | ch | ) |
Single ended conversion, polling mode (interrupt disabled).
ch | Select one of the ADC Input Channels (MUXA) or ADC Input Channels (MUXB). |
#define ADC_CH_DISABLE_CONFIG |
ADC module is disabled.