MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
AFE Channel Configuration Structures

Overview

This section describes default configuration structures for AFE channel. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define AFE_CH_HWTRG_CCM_PGAON_CONFIG(osr, gain)
 Selects hardware trigger continuous conversion mode. PGA is enabled and set to the user gain selected by the user. More...
 
#define AFE_CH_SWTRG_CCM_PGAON_CONFIG(osr, gain)
 Selects software trigger continuous conversion mode. PGA is enabled and set to the user gain selected by the user. More...
 
#define AFE_CH_HWTRG_SCM_PGAON_CONFIG(osr, gain)
 Selects hardware trigger single conversion mode. PGA is enabled and set to the user gain selected by the user. More...
 
#define AFE_CH_SWTRG_SCM_PGAON_CONFIG(osr, gain)
 Selects software trigger single conversion mode. PGA is enabled and set to the user gain selected by the user. More...
 
#define AFE_CH_HWTRG_CCM_PGAOFF_CONFIG(osr)
 Selects hardware trigger continuous conversion mode. PGA is disabled. More...
 
#define AFE_CH_SWTRG_CCM_PGAOFF_CONFIG(osr)
 Selects software trigger continuous conversion mode. PGA is disabled. More...
 
#define AFE_CH_HWTRG_SCM_PGAOFF_CONFIG(osr)
 Selects hardware trigger single conversion mode. PGA is disabled. More...
 
#define AFE_CH_SWTRG_SCM_PGAOFF_CONFIG(osr)
 Selects software trigger single conversion mode. PGA is disabled. More...
 
#define AFE_CH_SWTRG_SCM_DEC_INT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_HWTRG_SCM_DEC_INT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_SWTRG_SCM_DEC_EXT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_HWTRG_SCM_DEC_EXT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_SWTRG_SCM_DEC_INT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_HWTRG_SCM_DEC_INT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_SWTRG_SCM_DEC_EXT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_HWTRG_SCM_DEC_EXT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_SWTRG_CCM_DEC_INT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_HWTRG_CCM_DEC_INT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_SWTRG_CCM_DEC_EXT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_HWTRG_CCM_DEC_EXT_PE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge. More...
 
#define AFE_CH_SWTRG_CCM_DEC_INT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_HWTRG_CCM_DEC_INT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_SWTRG_CCM_DEC_EXT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge. More...
 
#define AFE_CH_HWTRG_CCM_DEC_EXT_NE_CLK_BYPASS_CONFIG(osr)
 Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge. More...
 

Macro Definition Documentation

#define AFE_CH_HWTRG_CCM_PGAON_CONFIG (   osr,
  gain 
)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|SET(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(gain))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Selects hardware trigger continuous conversion mode. PGA is enabled and set to the user gain selected by the user.

Parameters
osrSelect one of the AFE Oversampling Ratios.
gainSelect one of the AFE PGA Gain Stages.
Note
Use this configuration structure only for AFE channels with built-in programmable gain amplifier (PGA)
#define AFE_CH_SWTRG_CCM_PGAON_CONFIG (   osr,
  gain 
)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|SET(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(gain))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Selects software trigger continuous conversion mode. PGA is enabled and set to the user gain selected by the user.

Parameters
osrSelect one of the AFE Oversampling Ratios.
gainSelect one of the AFE PGA Gain Stages.
Note
Use this configuration structure only for AFE channels with built-in programmable gain amplifier (PGA)
#define AFE_CH_HWTRG_SCM_PGAON_CONFIG (   osr,
  gain 
)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|SET(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(gain))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Selects hardware trigger single conversion mode. PGA is enabled and set to the user gain selected by the user.

Parameters
osrSelect one of the AFE Oversampling Ratios.
gainSelect one of the AFE PGA Gain Stages.
Note
Use this configuration structure only for AFE channels with built-in programmable gain amplifier (PGA)
#define AFE_CH_SWTRG_SCM_PGAON_CONFIG (   osr,
  gain 
)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|SET(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(gain))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Selects software trigger single conversion mode. PGA is enabled and set to the user gain selected by the user.

Parameters
osrSelect one of the AFE Oversampling Ratios.
gainSelect one of the AFE PGA Gain Stages.
Note
Use this configuration structure only for AFE channels with built-in programmable gain amplifier (PGA)
#define AFE_CH_HWTRG_CCM_PGAOFF_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Selects hardware trigger continuous conversion mode. PGA is disabled.

Parameters
osrSelect one of the AFE Oversampling Ratios.
Note
If applied for AFE channel with built-in programmable gain amplifier (PGA) then PGA on the channel will be disabled.
#define AFE_CH_SWTRG_CCM_PGAOFF_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Selects software trigger continuous conversion mode. PGA is disabled.

Parameters
osrSelect one of the AFE Oversampling Ratios.
Note
If applied for AFE channel with built-in programmable gain amplifier (PGA) then PGA on the channel will be disabled.
#define AFE_CH_HWTRG_SCM_PGAOFF_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Selects hardware trigger single conversion mode. PGA is disabled.

Parameters
osrSelect one of the AFE Oversampling Ratios.
Note
If applied for AFE channel with built-in programmable gain amplifier (PGA) then PGA on the channel will be disabled.
#define AFE_CH_SWTRG_SCM_PGAOFF_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|CLR(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ SET(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Selects software trigger single conversion mode. PGA is disabled.

Parameters
osrSelect one of the AFE Oversampling Ratios.
Note
If applied for AFE channel with built-in programmable gain amplifier (PGA) then PGA on the channel will be disabled.
#define AFE_CH_SWTRG_SCM_DEC_INT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_SCM_DEC_INT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_SCM_DEC_EXT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_SCM_DEC_EXT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_SCM_DEC_INT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_SCM_DEC_INT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_SCM_DEC_EXT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger single conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_SCM_DEC_EXT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ CLR(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger single conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_CCM_DEC_INT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_CCM_DEC_INT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked internally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_CCM_DEC_EXT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_CCM_DEC_EXT_PE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|CLR(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked externally while registering input data on the rising (positive) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_CCM_DEC_INT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_CCM_DEC_INT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked internally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_SWTRG_CCM_DEC_EXT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ CLR(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to software trigger continuous conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.
#define AFE_CH_HWTRG_CCM_DEC_EXT_NE_CLK_BYPASS_CONFIG (   osr)
Value:
(tAFE_CH){ \
/* CFR */ SET(AFE_CFR_DEC_OSR(osr))|CLR(AFE_CFR_PGA_EN_MASK)| \
/* ... */ SET(AFE_CFR_PGA_GAIN_SEL(1))|SET(AFE_CFR_BYP_MODE_MASK)| \
/* ... */ CLR(AFE_CFR_SD_MOD_EN_MASK)|SET(AFE_CFR_DEC_EN_MASK)| \
/* ... */ SET(AFE_CFR_CC_MASK)|SET(AFE_CFR_DEC_CLK_EDGE_SEL_MASK)| \
/* ... */ SET(AFE_CFR_DEC_CLK_INP_SEL_MASK)| \
/* ... */ SET(AFE_CFR_HW_TRG_MASK), \
}

Modulator bypass mode with SD modulator and PGA blocks disabled. The wrapper is set to hardware trigger continuous conversion mode. Decimator is clocked externally while registering input data on the falling (negative) clock edge.

Parameters
osrSelect one of the AFE Oversampling Ratios.