MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
ADC Channel Configuration Structures

Overview

This section describes default configuration structures for ADC channel (result & status and control register). The 16-bit SAR ADC module on MKM34Z256VLx7 devices contains 4 result registers.

Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define ADC_CH_SE_IRQ_CONFIG(ch)
 Single ended conversion, interrupt enabled. More...
 
#define ADC_CH_SE_POLL_CONFIG(ch)
 Single ended conversion, polling mode (interrupt disabled). More...
 
#define ADC_CH_DISABLE_CONFIG
 ADC module is disabled. More...
 

Macro Definition Documentation

#define ADC_CH_SE_IRQ_CONFIG (   ch)
Value:
(tADC_CH){ \
/* SC1 */ SET(ADC_SC1_AIEN_MASK)|ch, \
}

Single ended conversion, interrupt enabled.

Parameters
chSelect one of the ADC Input Channels (MUXA) or ADC Input Channels (MUXB).
#define ADC_CH_SE_POLL_CONFIG (   ch)
Value:
(tADC_CH){ \
/* SC1 */ CLR(ADC_SC1_AIEN_MASK)|ch, \
}

Single ended conversion, polling mode (interrupt disabled).

Parameters
chSelect one of the ADC Input Channels (MUXA) or ADC Input Channels (MUXB).
#define ADC_CH_DISABLE_CONFIG
Value:
(tADC_CH){ \
/* SC1 */ CLR(ADC_SC1_AIEN_MASK)|AD_OFF, \
}

ADC module is disabled.

Note
Use either ADC_CH_SE_POLL_CONFIG or ADC_CH_SE_IRQ_CONFIG to perform ADC conversion on given channel.