MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
RCM Reset Sources

Overview

List of reset sources.

Macros

#define RCM_SACKERR
 Reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode after an attempt to enter Stop mode.
 
#define RCM_MDM_AP
 Reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register.
 
#define RCM_SW
 Reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core.
 
#define RCM_LOCKUP
 Reset has been caused by the ARM core indication of a LOCKUP event.
 
#define RCM_POR
 Reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold.
 
#define RCM_PIN
 Reset has been caused by an active-low level on the external /RESET pin.
 
#define RCM_WDOG
 Reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog.
 
#define RCM_LOL
 Reset has been caused by a loss of lock in the MCG PLL.
 
#define RCM_LOC
 Reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected.
 
#define RCM_LVD
 If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR.
 
#define RCM_WAKEUP
 Reset has been caused by an enabled wakeup source while the chip was in a low leakage mode. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except WAKEUP.