MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
WDOG Configuration Structures

Overview

This section describes default configuration structures for WDOG module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define WDOG_MODULE_NORMAL_STOP_DI_DBG_DI_CONFIG(clksrc, clkdiv, period)
 Enables watchdog module in normal (Timer) configuration. Watchdog is active in RUN, VLPR and WAIT modes. It doesn't run in STOP and DBG modes. More...
 
#define WDOG_MODULE_WINDOW_STOP_DI_DBG_DI_CONFIG(clksrc, clkdiv, per_hi, per_lo)
 Enables watchdog module in windowed configuration. Watchdog is active in RUN, VLPR and WAIT modes. It doesn't run in STOP and DBG modes. More...
 
#define WDOG_MODULE_NORMAL_STOP_EN_DBG_DI_CONFIG(clksrc, clkdiv, period)
 Enables watchdog module in normal (Timer) configuration. Watchdog is active in RUN, VLPR, WAIT and STOP modes. It doesn't run in DBG mode. More...
 
#define WDOG_MODULE_WINDOW_STOP_EN_DBG_DI_CONFIG(clksrc, clkdiv, per_hi, per_lo)
 Enables watchdog module in windowed configuration. Watchdog is active in RUN, VLPR, WAIT and STOP modes. It doesn't run in DBG mode. More...
 
#define WDOG_MODULE_NORMAL_STOP_DI_DBG_EN_CONFIG(clksrc, clkdiv, period)
 Enables watchdog module in normal (Timer) configuration. Watchdog is active in RUN, VLPR, WAIT and DBG modes. It doesn't run in STOP mode. More...
 
#define WDOG_MODULE_WINDOW_STOP_DI_DBG_EN_CONFIG(clksrc, clkdiv, per_hi, per_lo)
 Enables watchdog module in windowed configuration. Watchdog is active in RUN, VLPR, DBG and WAIT modes. It doesn't run in STOP mode. More...
 
#define WDOG_MODULE_NORMAL_STOP_EN_DBG_EN_CONFIG(clksrc, clkdiv, period)
 Enables watchdog module in normal (Timer) configuration. Watchdog is active in RUN, VLPR, WAIT, DBG and STOP modes. More...
 
#define WDOG_MODULE_WINDOW_STOP_EN_DBG_EN_CONFIG(clksrc, clkdiv, per_hi, per_lo)
 Enables watchdog module in windowed configuration. Watchdog is active in RUN, VLPR, WAIT, DBG and STOP modes. More...
 

Macro Definition Documentation

#define WDOG_MODULE_NORMAL_STOP_DI_DBG_DI_CONFIG (   clksrc,
  clkdiv,
  period 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
/* ....... */ SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((period>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((period>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH(0x00)), \
/* WINL */ SET(WDOG_WINL_WINLOW(0x00)), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is disabled in CPU Stop mode
  • WDOG is disabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is disabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    periodWatchdog timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_WINDOW_STOP_DI_DBG_DI_CONFIG (   clksrc,
  clkdiv,
  per_hi,
  per_lo 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((per_hi>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((per_hi>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH((uint16)((per_lo>>16)&0xffff))), \
/* WINL */ SET(WDOG_WINL_WINLOW((uint16)((per_lo>> 0)&0xffff))), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is disabled in CPU Stop mode
  • WDOG is disabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is enabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    per_hiUpper watchdog window timeout in number of clock cycles (4 to 4294967296).
    per_loLower watchdog window timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_NORMAL_STOP_EN_DBG_DI_CONFIG (   clksrc,
  clkdiv,
  period 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((period>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((period>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH(0x00)), \
/* WINL */ SET(WDOG_WINL_WINLOW(0x00)), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is enabled in CPU Stop mode
  • WDOG is disabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is disabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    periodWatchdog timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_WINDOW_STOP_EN_DBG_DI_CONFIG (   clksrc,
  clkdiv,
  per_hi,
  per_lo 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
/* ....... */ SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((per_hi>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((per_hi>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH((uint16)((per_lo>>16)&0xffff))), \
/* WINL */ SET(WDOG_WINL_WINLOW((uint16)((per_lo>> 0)&0xffff))), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is enabled in CPU Stop mode
  • WDOG is disabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is enabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    per_hiUpper watchdog window timeout in number of clock cycles (4 to 4294967296).
    per_loLower watchdog window timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_NORMAL_STOP_DI_DBG_EN_CONFIG (   clksrc,
  clkdiv,
  period 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
/* ....... */ SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((period>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((period>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH(0x00)), \
/* WINL */ SET(WDOG_WINL_WINLOW(0x00)), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is disabled in CPU Stop mode
  • WDOG is enabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is disabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    periodWatchdog timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_WINDOW_STOP_DI_DBG_EN_CONFIG (   clksrc,
  clkdiv,
  per_hi,
  per_lo 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((per_hi>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((per_hi>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH((uint16)((per_lo>>16)&0xffff))), \
/* WINL */ SET(WDOG_WINL_WINLOW((uint16)((per_lo>> 0)&0xffff))), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is disabled in CPU Stop mode
  • WDOG is enabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is enabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    per_hiUpper watchdog window timeout in number of clock cycles (4 to 4294967296).
    per_loLower watchdog window timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_NORMAL_STOP_EN_DBG_EN_CONFIG (   clksrc,
  clkdiv,
  period 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((period>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((period>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH(0x00)), \
/* WINL */ SET(WDOG_WINL_WINLOW(0x00)), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is enabled in CPU Stop mode
  • WDOG is enabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is disabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    periodWatchdog timeout in number of clock cycles (4 to 4294967296).
#define WDOG_MODULE_WINDOW_STOP_EN_DBG_EN_CONFIG (   clksrc,
  clkdiv,
  per_hi,
  per_lo 
)
Value:
(tWDOG){ \
/* STCTRLH */ SET(WDOG_STCTRLH_DISTESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_BYTESEL(0x00))| \
/* ....... */ CLR(WDOG_STCTRLH_TESTSEL_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_TESTWDOG_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_STOPEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_DBGEN_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_ALLOWUPDATE_MASK)| \
/* ....... */ SET(WDOG_STCTRLH_WINEN_MASK)| \
/* ....... */ CLR(WDOG_STCTRLH_IRQRSTEN_MASK)| \
/* ....... */ SET(clksrc<<WDOG_STCTRLH_CLKSRC_SHIFT)| \
/* ....... */ SET(WDOG_STCTRLH_WDOGEN_MASK), \
/* TOVALH */ SET(WDOG_TOVALH_TOVALHIGH((uint16)((per_hi>>16)&0xffff))), \
/* TOVALL */ SET(WDOG_TOVALL_TOVALLOW((uint16)((per_hi>> 0)&0xffff))), \
/* WINH */ SET(WDOG_WINH_WINHIGH((uint16)((per_lo>>16)&0xffff))), \
/* WINL */ SET(WDOG_WINL_WINLOW((uint16)((per_lo>> 0)&0xffff))), \
/* PRESC */ SET(WDOG_PRESC_PRESCVAL((clkdiv&0x07))), \
}

Enables watchdog module in normal (Timer) configuration with the following characteristic:

  • WDOG functional test mode is disabled permanently until reset
  • WDOG is enabled in CPU Wait mode
  • WDOG is enabled in CPU Stop mode
  • WDOG is enabled in CPU Debug mode
  • WDOG write-once registers can be unlocked for updating
  • Windowing mode is enabled
  • WDOG time-out generates reset only
  • WDOG is enabled
    Parameters
    clksrcSelect one of the WDOG Clock Sources.
    clkdivSelect one of the WDOG Clock Dividers.
    per_hiUpper watchdog window timeout in number of clock cycles (4 to 4294967296).
    per_loLower watchdog window timeout in number of clock cycles (4 to 4294967296).