MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
UART Configuration Structures

Overview

This section describes default configuration structures for UART module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define UART_MODULE_POLLMODE_CONFIG(brate, clk)
 Configures UART to operate in polling mode. Receive and transmit data is not inverted. More...
 
#define UART_MODULE_POLLMODE_TXINV_CONFIG(brate, clk)
 Configures UART to operate in polling mode. Receive data is not inverted. Transmit data is inverted. More...
 
#define UART_MODULE_INTRMODE_CONFIG(brate, clk)
 Configures UART to operate in interrupt mode. Receive and transmit data is not inverted. More...
 
#define UART_MODULE_INTRMODE_TXINV_CONFIG(brate, clk)
 Configures UART to operate in interrupt mode. Receive data is not inverted. Transmit data is inverted. More...
 

Macro Definition Documentation

#define UART_MODULE_POLLMODE_CONFIG (   brate,
  clk 
)
Value:
(tUART){ \
/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
/* BDL */ ((CALC_SBR(brate,clk)>>0)&0xff), \
/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \
/* ... */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \
/* ... */ CLR(UART_C1_ILT_MASK)|CLR(UART_C1_PE_MASK)| \
/* ... */ CLR(UART_C1_PT_MASK), \
/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \
/* ... */ CLR(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)| \
/* ... */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)| \
/* ... */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK), \
/* S2 */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)| \
/* ... */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)| \
/* ... */ CLR(UART_S2_BRK13_MASK), \
/* C3 */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)| \
/* ... */ CLR(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)| \
/* ... */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)| \
/* ... */ CLR(UART_C3_PEIE_MASK), \
/* MA1 */ SET(UART_MA1_MA(0x00)), \
/* MA2 */ SET(UART_MA2_MA(0x00)), \
/* C4 */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)| \
/* ... */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
/* C5 */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK) \
}

Configures UART to operate in polling mode. Receive and transmit data is not inverted.

Parameters
brateBaud rate.
clkModule clock in Hz:
UART0 UART1 UART2 UART3
Bus clockSystem clockBus clockSystem clock
#define UART_MODULE_POLLMODE_TXINV_CONFIG (   brate,
  clk 
)
Value:
(tUART){ \
/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
/* BDL */ ((CALC_SBR(brate,clk)>>0)&0xff), \
/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \
/* ... */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \
/* ... */ CLR(UART_C1_ILT_MASK)|CLR(UART_C1_PE_MASK)| \
/* ... */ CLR(UART_C1_PT_MASK), \
/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \
/* ... */ CLR(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)| \
/* ... */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)| \
/* ... */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK), \
/* S2 */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)| \
/* ... */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)| \
/* ... */ CLR(UART_S2_BRK13_MASK), \
/* C3 */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)| \
/* ... */ SET(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)| \
/* ... */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)| \
/* ... */ CLR(UART_C3_PEIE_MASK), \
/* MA1 */ SET(UART_MA1_MA(0x00)), \
/* MA2 */ SET(UART_MA2_MA(0x00)), \
/* C4 */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)| \
/* ... */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
/* C5 */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK) \
}

Configures UART to operate in polling mode. Receive data is not inverted. Transmit data is inverted.

Parameters
brateBaud rate.
clkModule clock in Hz:
UART0 UART1 UART2 UART3
Bus clockSystem clockBus clockSystem clock
#define UART_MODULE_INTRMODE_CONFIG (   brate,
  clk 
)
Value:
(tUART){ \
/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
/* BDL */ ((CALC_SBR(brate,clk)>>0)&0xff), \
/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \
/* ... */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \
/* ... */ CLR(UART_C1_ILT_MASK)|CLR(UART_C1_PE_MASK)| \
/* ... */ CLR(UART_C1_PT_MASK), \
/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \
/* ... */ SET(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)| \
/* ... */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)| \
/* ... */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK), \
/* S2 */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)| \
/* ... */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)| \
/* ... */ CLR(UART_S2_BRK13_MASK), \
/* C3 */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)| \
/* ... */ CLR(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)| \
/* ... */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)| \
/* ... */ CLR(UART_C3_PEIE_MASK), \
/* MA1 */ SET(UART_MA1_MA(0x00)), \
/* MA2 */ SET(UART_MA2_MA(0x00)), \
/* C4 */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)| \
/* ... */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
/* C5 */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK) \
}

Configures UART to operate in interrupt mode. Receive and transmit data is not inverted.

Parameters
brateBaud rate.
clkModule clock in Hz:
UART0 UART1 UART2 UART3
Bus clockSystem clockBus clockSystem clock
#define UART_MODULE_INTRMODE_TXINV_CONFIG (   brate,
  clk 
)
Value:
(tUART){ \
/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,clk)>>8)&0x1f), \
/* BDL */ ((CALC_SBR(brate,clk)>>0)&0xff), \
/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \
/* ... */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \
/* ... */ CLR(UART_C1_ILT_MASK)|CLR(UART_C1_PE_MASK)| \
/* ... */ CLR(UART_C1_PT_MASK), \
/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \
/* ... */ SET(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)| \
/* ... */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)| \
/* ... */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK), \
/* S2 */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)| \
/* ... */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)| \
/* ... */ CLR(UART_S2_BRK13_MASK), \
/* C3 */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)| \
/* ... */ SET(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)| \
/* ... */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)| \
/* ... */ CLR(UART_C3_PEIE_MASK), \
/* MA1 */ SET(UART_MA1_MA(0x00)), \
/* MA2 */ SET(UART_MA2_MA(0x00)), \
/* C4 */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)| \
/* ... */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,clk)>>0)&0x1f), \
/* C5 */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK) \
}

Configures UART to operate in interrupt mode. Receive data is not inverted. Transmit data is inverted.

Parameters
brateBaud rate.
clkModule clock in Hz:
UART0 UART1 UART2 UART3
Bus clockSystem clockBus clockSystem clock