MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
VREF Switch Control Configuration Structures

Overview

This section describes default configuration structures for VREF switch control. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

VREF configuration:
vref_block.jpg

Macros

#define VREF_SWITCH_S1_L_S2_L_S3_L_BUFF_EN
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_H_S2_L_S3_L_BUFF_EN
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_H_S3_L_BUFF_EN
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_H_S3_H_BUFF_EN
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_L_S3_L_BUFF_DI
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_H_S3_L_BUFF_DI
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_H_S3_H_BUFF_DI
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_L_S3_H_BUFF_DI
 Voltage reference switch setting. More...
 
#define VREF_SWITCH_S1_L_S2_L_S3_H_BUFF_EN
 Voltage reference switch setting. More...
 

Macro Definition Documentation

#define VREF_SWITCH_S1_L_S2_L_S3_L_BUFF_EN
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ CLR(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer enable,
  • Buffer does not drive PAD, S1 = L,
  • Internal reference select, S2 = L,
  • AFE Internal reference select, S3 = L,
#define VREF_SWITCH_S1_H_S2_L_S3_L_BUFF_EN
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ SET(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ CLR(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer enable,
  • Buffer drive voltage on PAD, S1 = H,
  • Internal reference select, S2 = L,
  • AFE Internal reference select, S3 = L,
#define VREF_SWITCH_S1_L_S2_H_S3_L_BUFF_EN
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ SET(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ CLR(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer enable,
  • Buffer does not drive PAD, S1 = L,
  • External reference select, S2 = H,
  • AFE Internal reference select, S3 = L,
#define VREF_SWITCH_S1_L_S2_H_S3_H_BUFF_EN
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ SET(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ SET(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer enable,
  • Buffer does not drive PAD, S1 = L,
  • External reference select, S2 = H,
  • AFE External reference select, S3 = H,
#define VREF_SWITCH_S1_L_S2_L_S3_L_BUFF_DI
Value:
(tVREF_S){ \
/* SIM_MISC */ SET(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ CLR(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer disabled,
  • Buffer does not drive PAD, S1 = L,
  • Internal reference select, S2 = L,
  • AFE Internal reference select, S3 = L,
#define VREF_SWITCH_S1_L_S2_H_S3_L_BUFF_DI
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ SET(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ CLR(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer disabled,
  • Buffer does not drive PAD, S1 = L,
  • External reference select, S2 = H,
  • AFE Internal reference select, S3 = L,
#define VREF_SWITCH_S1_L_S2_H_S3_H_BUFF_DI
Value:
(tVREF_S){ \
/* SIM_MISC */ SET(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ SET(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ SET(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer disabled,
  • Buffer does not drive PAD, S1 = L,
  • External reference select, S2 = H,
  • AFE External reference select, S3 = H,
#define VREF_SWITCH_S1_L_S2_L_S3_H_BUFF_DI
Value:
(tVREF_S){ \
/* SIM_MISC */ SET(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ SET(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer disabled,
  • Buffer does not drive PAD, S1 = L,
  • Internal reference select, S2 = L,
  • AFE External reference select, S3 = H,
#define VREF_SWITCH_S1_L_S2_L_S3_H_BUFF_EN
Value:
(tVREF_S){ \
/* SIM_MISC */ CLR(SIM_MISC_CTL_VREFBUFPD_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFINSEL_MASK)| \
/* ......... */ CLR(SIM_MISC_CTL_VREFBUFOUTEN_MASK), \
/* VERFL_TRM */ SET(VREF_VREFL_TRM_VREFL_SEL_MASK), \
}

Configures voltage reference switches:

  • Buffer enabled,
  • Buffer does not drive PAD, S1 = L,
  • Internal reference select, S2 = L,
  • AFE External reference select, S3 = H,