MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
TMR Configuration Structures

Overview

This section describes default configuration structures for TMR module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define TMR_CH_CNTR_DI_CONFIG1(prm_clk_src, sec_clk_src)
 Configures Timer/Counter Mode - Rollover. More...
 
#define TMR_CH_CNTR_EN_CONFIG1(prm_clk_src, sec_clk_src)
 Enables Timer/Counter Mode - Rollover. More...
 
#define TMR_CH_CNTR_DI_CONFIG2(prm_clk_src, sec_clk_src)
 Configures Timer/Counter Mode - One Shot. More...
 
#define TMR_CH_CNTR_EN_CONFIG2(prm_clk_src, sec_clk_src)
 Enables Timer/Counter Mode - One Shot. More...
 
#define TMR_CH_CNTR_DI_CONFIG3(prm_clk_src, sec_clk_src)
 Configures Simple Timer/Counter Mode. More...
 
#define TMR_CH_CNTR_EN_CONFIG3(prm_clk_src, sec_clk_src)
 Enables Simple Timer/Counter Mode. More...
 
#define TMR_CH_CNTR_DI_CONFIG4(prm_clk_src, sec_clk_src)
 Configures Simple Timer/Counter Mode. More...
 
#define TMR_CH_CNTR_EN_CONFIG4(prm_clk_src, sec_clk_src)
 Enables Simple Timer/Counter Mode. More...
 
#define TMR_CH_CAPT_DI_CONFIG1(prm_clk_src, sec_clk_src, input_mode)
 Configures Input Capture Mode. More...
 
#define TMR_CH_CAPT_EN_CONFIG1(prm_clk_src, sec_clk_src, input_mode)
 Enables Input Capture Mode. More...
 
#define TMR_CH_CAPT_DI_CONFIG2(prm_clk_src, sec_clk_src, input_mode)
 Configures Input Capture Mode. More...
 
#define TMR_CH_CAPT_EN_CONFIG2(prm_clk_src, sec_clk_src, input_mode)
 Enables Input Capture Mode. More...
 
#define TMR_CH_OUTCMP_DI_CONFIG(count_mode, prm_clk_src, sec_clk_src, output_mode)
 Configures Output Compare Mode. More...
 
#define TMR_CH_OUTCMP_EN_CONFIG(count_mode, prm_clk_src, sec_clk_src, output_mode)
 Enables Output Compare Mode. More...
 

Macro Definition Documentation

#define TMR_CH_CNTR_DI_CONFIG1 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Timer/Counter Mode - Rollover. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The Timer is configured in Counter Mode with following the characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_EN_CONFIG1 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Timer/Counter Mode - Rollover. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The Timer is configured in Counter Mode with following the characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_DI_CONFIG2 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ SET(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Timer/Counter Mode - One Shot. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode enabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_EN_CONFIG2 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ SET(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Timer/Counter Mode - One Shot. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode enabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_DI_CONFIG3 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ SET(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize
  • One shot Timer mode enabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_EN_CONFIG3 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ SET(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize
  • One shot Timer mode enabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_DI_CONFIG4 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CNTR_EN_CONFIG4 (   prm_clk_src,
  sec_clk_src 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
#define TMR_CH_CAPT_DI_CONFIG1 (   prm_clk_src,
  sec_clk_src,
  input_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ CLR(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ SET(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(input_mode))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt disabled
  • Input capture interrupt enabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    input_modeSelect one of the TMR Input Capture Modes.
#define TMR_CH_CAPT_EN_CONFIG1 (   prm_clk_src,
  sec_clk_src,
  input_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ CLR(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ SET(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(input_mode))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt disabled
  • Input capture interrupt enabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    input_modeSelect one of the TMR Input Capture Modes.
#define TMR_CH_CAPT_DI_CONFIG2 (   prm_clk_src,
  sec_clk_src,
  input_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ CLR(TMR_SCTRL_TCFIE_MASK)|SET(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ SET(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(input_mode))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt enabled
  • Co-channel initialization disabled
  • Compare interrupt disabled
  • Input capture interrupt enabled
  • Input signal polarity not inverted
  • Timer channel is disabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    input_modeSelect one of the TMR Input Capture Modes.
#define TMR_CH_CAPT_EN_CONFIG2 (   prm_clk_src,
  sec_clk_src,
  input_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(COUNT_POSEDGE))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))|\
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|CLR(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(ASSERT_ON_CNTR_ACTIVE)), \
/* SCTRL */ CLR(TMR_SCTRL_TCFIE_MASK)|SET(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ SET(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(input_mode))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:

  • Counts up
  • Rollover enabled
  • One shot Timer mode disabled
  • Overflow interrupt enabled
  • Co-channel initialization disabled
  • Compare interrupt disabled
  • Input capture interrupt enabled
  • Input signal polarity not inverted
  • Timer channel is enabled
    Parameters
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    input_modeSelect one of the TMR Input Capture Modes.
#define TMR_CH_OUTCMP_DI_CONFIG (   count_mode,
  prm_clk_src,
  sec_clk_src,
  output_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(count_mode))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))| \
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(output_mode)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(0)), \
}

Configures Output Compare Mode. The timer operates in Output Compare Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize.
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Master operation disabled
  • External OFLAG force disabled.
  • Polarity of OFLAG output signal not inverted.
  • Output not forced to external pin
  • Timer channel is disabled
    Parameters
    count_modeSelect one of the TMR Count Modes.
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    output_modeSelect one of the TMR OFLAG Signal Modes.
#define TMR_CH_OUTCMP_EN_CONFIG (   count_mode,
  prm_clk_src,
  sec_clk_src,
  output_mode 
)
Value:
(tTMR_CH){ \
/* CTRL */ SET(TMR_CTRL_CM(count_mode))| \
/* ...... */ SET(TMR_CTRL_PCS(prm_clk_src))|SET(TMR_CTRL_SCS(sec_clk_src))| \
/* ...... */ CLR(TMR_CTRL_DIR_MASK)|SET(TMR_CTRL_LENGTH_MASK)| \
/* ...... */ CLR(TMR_CTRL_ONCE_MASK)|CLR(TMR_CTRL_COINIT_MASK)| \
/* ...... */ SET(TMR_CTRL_OUTMODE(output_mode)), \
/* SCTRL */ SET(TMR_SCTRL_TCFIE_MASK)|CLR(TMR_SCTRL_TOFIE_MASK)| \
/* ...... */ CLR(TMR_SCTRL_IEFIE_MASK)|CLR(TMR_SCTRL_IPS_MASK)| \
/* ...... */ SET(TMR_SCTRL_CAPTURE_MODE(CAPTURE_DISABLED))| \
/* ...... */ CLR(TMR_SCTRL_MSTR_MASK)|CLR(TMR_SCTRL_EEOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_VAL_MASK)|CLR(TMR_SCTRL_TOF_MASK)| \
/* ...... */ CLR(TMR_SCTRL_OPS_MASK)|CLR(TMR_SCTRL_OEN_MASK), \
/* CSCTRL */ SET(TMR_CSCTRL_DBG_EN(0))|CLR(TMR_CSCTRL_FAULT_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_ALT_LOAD_MASK)|CLR(TMR_CSCTRL_ROC_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCI_MASK)|CLR(TMR_CSCTRL_TCF2EN_MASK)| \
/* ...... */ CLR(TMR_CSCTRL_TCF1EN_MASK)|SET(TMR_CSCTRL_CL2(0))| \
/* ...... */ SET(TMR_CSCTRL_CL1(0)), \
/* ENBL */ SET(TMR_ENBL_ENBL(15)), \
}

Enables Output Compare Mode. The timer operates in Output Compare Mode with the following characteristics:

  • Counts up
  • Count until compare then re-initialize.
  • One shot Timer mode disabled
  • Overflow interrupt disabled
  • Co-channel initialization disabled
  • Compare interrupt enabled
  • Input capture interrupt disabled
  • Input signal polarity not inverted
  • Master operation disabled
  • External OFLAG force disabled.
  • Polarity of OFLAG output signal not inverted.
  • Output not forced to external pin
  • Timer channel is enabled
    Parameters
    count_modeSelect one of the TMR Count Modes.
    prm_clk_srcSelect one of the TMR Primary Count Sources.
    sec_clk_srcSelect one of the TMR Secondary Count Sources.
    output_modeSelect one of the TMR OFLAG Signal Modes.