This section describes functions and macros of the driver's API.
#define PLL_Enable |
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clk | ) |
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This macro selects PLL 32KHz reference clock and enables PLL module. PLL is enabled by setting PLLCLKEN0 bit.
- Parameters
-
- Note
- Implemented as an inline macro.
- Warning
- FLL or PLL is enabled by this macro (LP bit is deasserted). The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set.
- See also
- PLL_Disable, SIM_CtrlPLLVLP, PLL_CtrlPLLSTEN
This macro disables PLL module by clearing MCG_C5[PLLCLKEN0] and setting MCG_C2[LP] bits.
- Note
- Implemented as an inline macro.
- See also
- PLL_Enable
#define PLL_CtrlPLLSTEN |
( |
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x | ) |
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This macro enables/disables PLL operation during normal stop mode by setting/clearing PLLSTEN0 bit, respectively.
- Parameters
-
x | TRUE (MCGPLLCLK is enabled if system is in normal Stop mode)
FALSE (MCGPLLCLK is disabled in any of the Stop modes). |
- Note
- Implemented as an inline macro.
- Warning
- In Low Power Stop mode, the PLL clock gets disabled even if PLL operation was enabled using this macro. In all other power modes PLLSTEN0 bit has no affect and does not enable the PLL operation.
- See also
- PLL_Enable, PLL_Init, SIM_CtrlPLLVLP