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MKMxxZxxACxx5 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes functions and macros of the driver's API.
Macros | |
#define | TMR_Disable(mask) |
Disables operation of the selected Timer channel(s). More... | |
#define | TMR_Enable(mask) |
Enables operation of the selected Timer channel(s). More... | |
#define | TMR_SetCmp1Val(ch, val) |
Sets COMP1 register. More... | |
#define | TMR_SetCmp2Val(ch, val) |
Sets COMP2 register. More... | |
#define | TMR_SetCountMode(ch, mode) |
Sets count mode. More... | |
#define | TMR_SetOutMode(ch, mode) |
Determines the mode of operation for the OFLAG output signal. More... | |
#define | TMR_GetOutMode(ch) |
Returns the mode of operation for the OFLAG output signal. More... | |
#define | TMR_ForceOFLAG(ch, val) |
Forces value passed by input argument to OFLAG output signal. More... | |
#define | TMR_SetPrmClkSrc(ch, src) |
Sets primary clock source. More... | |
#define | TMR_SetLoadVal(ch, val) |
Sets LOAD register. More... | |
#define | TMR_SetHoldVal(ch, val) |
Sets HOLD register. More... | |
#define | TMR_SetCntrVal(ch, val) |
Sets CNTR register. More... | |
#define | TMR_SetCmpLoad1Val(ch, val) |
Sets CMPLD1 register. More... | |
#define | TMR_SetCmpLoad2Val(ch, val) |
Sets CMPLD2 register. More... | |
#define | TMR_GetCaptVal(ch) |
Returns val of the CAPTURE register. More... | |
#define | TMR_ReadClrCaptReg(ch, ptr) |
Reads value of the CAPTURE register if input edge flag was set and clears input edge flag. More... | |
#define | TMR_GetCntrVal(ch) |
Returns value of the COUNTER register. More... | |
#define | TMR_GetINPUT(ch) |
Returns current state of the external input pin. More... | |
#define | TMR_CtrlOEN(ch, x) |
Configures the direction of the external pin. More... | |
#define | TMR_CtrlOPS(ch, x) |
Configures the polarity of the OFLAG output signal. More... | |
#define | TMR_SetScsFilter(ch, cnt, per) |
Configures quad timer channel secondary count source input filter. More... | |
#define | TMR_Init(ch, cfg, comp1, comp2, load, cmpld1, cmpld2, ip, callback) |
TMR channel initialization. More... | |
#define TMR_Disable | ( | mask | ) |
This macro disables operation of the selected Timer channel(s).
mask | Select one or more OR'ed Generic Peripheral Channels. |
#define TMR_Enable | ( | mask | ) |
This macro enables operation of the selected Timer channel(s).
mask | Select one or more OR'ed Generic Peripheral Channels. |
#define TMR_SetCmp1Val | ( | ch, | |
val | |||
) |
This macro sets COMP1 register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 COMP1 register value. |
#define TMR_SetCmp2Val | ( | ch, | |
val | |||
) |
This macro sets COMP2 register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 COMP2 register value. |
#define TMR_SetCountMode | ( | ch, | |
mode | |||
) |
This macro sets count mode.
ch | CH0,CH1,CH2,CH3. |
mode | Select one of the TMR Count Modes. |
#define TMR_SetOutMode | ( | ch, | |
mode | |||
) |
This macro determines the mode of operation for the OFLAG output signal.
ch | CH0,CH1,CH2,CH3. |
mode | Select one of the TMR OFLAG Signal Modes. |
#define TMR_GetOutMode | ( | ch | ) |
This macro returns the mode of operation for the OFLAG output signal.
ch | CH0,CH1,CH2,CH3. |
#define TMR_ForceOFLAG | ( | ch, | |
val | |||
) |
This macro forces value passed by input argument to OFLAG output signal by asserting TMRx_SCTRL[FORCE]=1. When the FORCE bit is written with a 1, then the VAL bit value will be placed on the OFLAG. The FORCE command can be written at any time. The OFLAG is not held at the value of the VAL bit. The FORCE bit is write only and only transfers the value of the VAL bit to OFLAG in the cycle when the FORCE bit is written to.
ch | CH0,CH1,CH2,CH3. |
val | 1 (logic one) 0 (logic zero) |
#define TMR_SetPrmClkSrc | ( | ch, | |
src | |||
) |
This macro sets primary clock source.
ch | CH0,CH1,CH2,CH3. |
src | Select one of the TMR Primary Count Sources. |
#define TMR_SetLoadVal | ( | ch, | |
val | |||
) |
This macro sets LOAD register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 LOAD register value. |
#define TMR_SetHoldVal | ( | ch, | |
val | |||
) |
This macro sets HOLD register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 HOLD register value. |
#define TMR_SetCntrVal | ( | ch, | |
val | |||
) |
This macro sets CNTR register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 CNTR register value. |
#define TMR_SetCmpLoad1Val | ( | ch, | |
val | |||
) |
This macro sets CMPLD1 register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 CMPLD1 register value. |
#define TMR_SetCmpLoad2Val | ( | ch, | |
val | |||
) |
This macro sets CMPLD2 register.
ch | CH0,CH1,CH2,CH3. |
val | uint16 CMPLD2 register value. |
#define TMR_GetCaptVal | ( | ch | ) |
This macro returns value of the CAPTURE register.
ch | CH0,CH1,CH2,CH3. |
#define TMR_ReadClrCaptReg | ( | ch, | |
ptr | |||
) |
This inline function reads value of the CAPTURE register if input edge flag was set. It also clears input edge flag after successful read.
ch | CH0,CH1,CH2,CH3. |
ptr | Pointer to the uint16 value. |
#define TMR_GetCntrVal | ( | ch | ) |
This macro returns value of the COUNTER register.
ch | CH0,CH1,CH2,CH3. |
#define TMR_GetINPUT | ( | ch | ) |
This macro returns current state of the external input pin selected via the secondary count source after application of IPS and filtering.
ch | CH0,CH1,CH2,CH3. |
#define TMR_CtrlOEN | ( | ch, | |
x | |||
) |
This macro configures the direction of the external pin.
ch | CH0,CH1,CH2,CH3. |
x | TRUE The OFLAG output signal is driven on the external pin. The other timer groups using this external pin as their input see the driven value FALSE The external pin is configured as an input (default). |
#define TMR_CtrlOPS | ( | ch, | |
x | |||
) |
This macro configures the polarity of the OFLAG output signal.
ch | CH0,CH1,CH2,CH3. |
x | TRUE Inverted polarity FALSE True polarity (default). |
#define TMR_SetScsFilter | ( | ch, | |
cnt, | |||
per | |||
) |
This macro configures quad timer channel secondary count source input filter.
ch | CH0,CH1,CH2,CH3. |
cnt | Number of consecutive samples from 0 to 7 that must agree prior to the input filter accepting an input transition. A value of 0 represents 3 samples and value of 7 represents 10 samples. |
per | uint8 filter sampling period. Each input is sampled multiple times at the rate specified by this parameter. If per is 0 (default), then the input filter is bypassed. |
#define TMR_Init | ( | ch, | |
cfg, | |||
comp1, | |||
comp2, | |||
load, | |||
cmpld1, | |||
cmpld2, | |||
ip, | |||
callback | |||
) |
This function initializes channel of the TMR Timer selected by the input argument. It also installs callback function for interrupt vector associated with the initialized TMR channel: vector 23(CH0), vector 24(CH1), vector 25(CH2) and vector 26(CH3).
ch | CH0,CH1,CH2,CH3. |
cfg | Select one of the TMR Configuration Structures. |
comp1 | uint16 compare register 1 value. |
comp2 | uint16 compare register 2 value. |
load | uint16 load register value. |
cmpld1 | uint16 comparator load register 1 value. |
cmpld2 | uint16 comparator load register 1 value. |
ip | Select one of the ARM Cortex-M0+ Interrupt Priority Levels. |
callback | Pointer to the TMR Callback Function. |