MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
IRTC Fine Compensation Logic

The fine compensation logic is suitable for many 32.768 kHz crystals, and can correct a wide range of crystal offsets.

The software example initializes IRTC module including so called fine compensation logic, RTCCLKOUT pin to generate 1 Hz pulse output, and FreeMASTER interface to communicate through UART2 module (38400/8-N-1). It demonstrates capability of the IRTC module to output a precise 1 Hz pulse output signal (through RTCCLKOUT pin) that represents clock frequency used to drive IRTC's internal time and date counters. This 1 Hz pulse output signal is outputted by the fine compensation logic and is generated with high resolution of the clock edge placement (up to 0.88 ppm) and near 50% duty cycle as shown in Figure 1.

The software sets an integral compensation value, a 2's complement value of the integer part of correction or compensation value that has to be adjusted in every 1 second period, to value -5 (-152.59 ppm), and a fraction compensation value, a fractional part of the correction or compensation value that has to be adjusted in every 1 second period, to value 11 (+2.62 ppm). Note that, integral and fraction compensation values are expressed in terms of number of clock cycles of the 32.768 kHz oscillator clock (30.51 ppm) and fixed 4.194304 MHz clock (0.24 ppm), respectively.

Parameters of the 1 Hz pulse output generated by the fine compensation block.
rtcclkout_fine.bmp

You may modify integral and fractional compensation values using FreeMASTER interface in order to analyze their impact on frequency of the generated 1 Hz pulse output.

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* irtc1hzpulse_test.c
******************************************************************************/
#include "drivers.h"
#include "freemaster.h"
static int8 int_comp_val = -5;
static uint8 fra_comp_val = 11;
/* FreeMASTER TSA table */
FMSTR_TSA_TABLE_BEGIN(first_table)
FMSTR_TSA_RW_VAR(int_comp_val, FMSTR_TSA_SINT8)
FMSTR_TSA_RW_VAR(fra_comp_val, FMSTR_TSA_UINT8)
FMSTR_TSA_TABLE_END()
FMSTR_TSA_TABLE_LIST_BEGIN()
FMSTR_TSA_TABLE(first_table)
FMSTR_TSA_TABLE_LIST_END()
/* End of FreeMASTER TSA table */
void main (void)
{
/* initialize SIM module and enable MCGIRCLK for use by peripherals */
/* enable MCGIRCLK for use by peripherals and change MCGIRCLK clock */
/* frequency from 2.097 MHz to 4.192 MHz */
/* initialize IRTC with 1 Hz fine pulse output (routed to PTF2) */
IRTC_Init (IRTC_MODULE_COMP_FINE_CONFIG(LFSR_CLK_2HZ,0,int_comp_val,fra_comp_val),
0);
/* initialize UART and FreeMASTER */
FMSTR_Init();
while(1)
{
IRTC_UpdateFineCompVal (int_comp_val,fra_comp_val);
FMSTR_Poll ();
}
}
Freemaster_cfg.h:
/***************************************************************************/
#ifndef __FREEMASTER_CFG_H
#define __FREEMASTER_CFG_H
/******************************************************************************
* Select interrupt or poll-driven serial communication
*******************************************************************************/
#define FMSTR_LONG_INTR 0 /* complete msg processing in interrupt */
#define FMSTR_SHORT_INTR 0 /* SCI FIFO-queuing done in interrupt */
#define FMSTR_POLL_DRIVEN 1 /* no interrupt needed, polling only */
/******************************************************************************
* Select SCI communication interface
*******************************************************************************/
#define FMSTR_USE_SCI 1 /* To select SCI communication interface */
#define FMSTR_USE_PDBDM 0 /* To select Packet Driven BDM interface */
//#define FMSTR_SCI_BASE 0x4006A000 /* UART0 base on MKM34Z50 */
#define FMSTR_SCI_BASE 0x4006B000 /* UART1 base on MKM34Z50 */
//#define FMSTR_SCI_BASE 0x4006C000 /* UART2 base on MKM34Z50 */
//#define FMSTR_SCI_BASE 0x4006D000 /* UART3 base on MKM34Z50 */
/******************************************************************************
* Input/output communication buffer size
*******************************************************************************/
#define FMSTR_COMM_BUFFER_SIZE 200 /* set to 0 for "automatic" */
/******************************************************************************
* Receive FIFO queue size (use with FMSTR_SHORT_INTR only)
*******************************************************************************/
#define FMSTR_COMM_RQUEUE_SIZE 32 /* set to 0 for "default" */
/******************************************************************************
* Support for Application Commands
*******************************************************************************/
#define FMSTR_USE_APPCMD 0 /* enable/disable App.Commands support */
#define FMSTR_APPCMD_BUFF_SIZE 32 /* App.Command data buffer size */
#define FMSTR_MAX_APPCMD_CALLS 4 /* num. of app.cmd callbacks? (0=disable) */
/******************************************************************************
* Oscilloscope support
*******************************************************************************/
#define FMSTR_USE_SCOPE 1 /* enable/disable scope support */
#define FMSTR_MAX_SCOPE_VARS 8 /* max. number of scope variables (2..8) */
/******************************************************************************
* Recorder support
*******************************************************************************/
#define FMSTR_USE_RECORDER 1 /* enable/disable recorder support */
#define FMSTR_MAX_REC_VARS 8 /* max. num. of recorder variables (2..8) */
/* built-in recorder buffer (use when FMSTR_REC_OWNBUFF is 0) */
#define FMSTR_REC_BUFF_SIZE 4096 /* built-in buffer size */
/* recorder time base, specifies how often the recorder is called */
#define FMSTR_REC_TIMEBASE FMSTR_REC_BASE_MILLISEC(0) /* 0 = "unknown" */
#define FMSTR_REC_FLOAT_TRIG 0 /* enable/disable floating point trigger */
/******************************************************************************
* Target-side address translation (TSA)
*******************************************************************************/
#define FMSTR_USE_TSA 1 /* enable TSA functionality */
#define FMSTR_USE_TSA_SAFETY 1 /* enable access to TSA variables only */
#define FMSTR_USE_TSA_INROM 1 /* TSA tables as const (put to ROM) */
/******************************************************************************
* Enable the byte access to communication buffer. All Cortex M0-based devices
* require this option to be set in order to avoid misaligned access to integer
* parameters which is unsupported on this platform.
*******************************************************************************/
#define FMSTR_BYTE_BUFFER_ACCESS 1
#endif /* __FREEMASTER_CFG_H */
Toolchain support:
IAR EWARM 7.40.7CodeWarrior 10.6KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0