MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
PLL & FLL Engaged Controlled by 32.768 kHz RTCOSC

This example shows FLL Engaged External (FEE) and PLL Engaged External (PEE) modules clocked by 32.768 kHz RTC Oscillator. The FLL module usually generates faster clock than PLL and it is intended for driving system, core and flash blocks. The PLL module, low jitter clock source, drives Analogue Front-End (AFE).

Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* fllpll_test.c
******************************************************************************/
#include "drivers.h"
void main (void)
{
/* enable clocks to all peripherals - clock mode 2:1:1 (core:bus:flash) */
/* route core clock to PTF7 */
/* clock mode 1:1:1 */
/* FLL settings */
/* route PLL clock output from MCG to PTF7 */
/* Set 32 KHz RTC Oscillator as the source of the PLL and enable PLL */
PLL_CtrlPLLSTEN (FALSE); /* PLL will be disabled in Normal Stop Mode */
while(1);
}
Toolchain support:
IAR EWARM 7.40.7CodeWarrior 10.6KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0