MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
I2C Configuration Structures

Overview

This section describes default configuration structures for I2C module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define I2C_MODULE_IRQ_DI_CONFIG(icr)
 I2C configured to operate in pooling mode. More...
 
#define I2C_MODULE_IRQ_EN_CONFIG(icr)
 I2C configured to operate in interrupt mode. More...
 

Macro Definition Documentation

#define I2C_MODULE_IRQ_DI_CONFIG (   icr)
Value:
(tI2C){ \
/* A1 */ CLR(I2C_A1_AD(0)), \
/* F */ SET(I2C_F_MULT(0))|SET(I2C_F_ICR(icr)), \
/* C1 */ SET(I2C_C1_IICEN_MASK)|CLR(I2C_C1_IICIE_MASK)| \
/* .... */ CLR(I2C_C1_MST_MASK)|CLR(I2C_C1_TX_MASK)| \
/* .... */ CLR(I2C_C1_TXAK_MASK)|CLR(I2C_C1_RSTA_MASK)| \
/* .... */ CLR(I2C_C1_WUEN_MASK)|CLR(I2C_C1_DMAEN_MASK), \
/* C2 */ CLR(I2C_C2_GCAEN_MASK)|CLR(I2C_C2_ADEXT_MASK)| \
/* .... */ CLR(I2C_C2_HDRS_MASK)|CLR(I2C_C2_SBRC_MASK)| \
/* .... */ CLR(I2C_C2_RMEN_MASK)|CLR(I2C_C2_AD(0)), \
/* FLT */ CLR(I2C_FLT_FLT(0)), \
/* RA */ CLR(I2C_RA_RAD(0)), \
/* SMB */ CLR(I2C_SMB_FACK_MASK)|CLR(I2C_SMB_ALERTEN_MASK)| \
/* .... */ CLR(I2C_SMB_SIICAEN_MASK)|CLR(I2C_SMB_TCKSEL_MASK)| \
/* .... */ CLR(I2C_SMB_SLTF_MASK)|CLR(I2C_SMB_SHTF2_MASK)| \
/* .... */ CLR(I2C_SMB_SHTF2IE_MASK), \
/* A2 */ CLR(I2C_A2_SAD(0)), \
/* SLTH */ CLR(I2C_SLTH_SSLT(0)), \
/* SLTL */ CLR(I2C_SLTL_SSLT(0)) \
}

Module is enabled after initialization, master mode, IRQ disabled.\

Parameters
icrclock rate (see also "I2C divider and hold values" table in RD).
Note
I2C baud rates selector:
Baud rate [kBps]Bus clock [MHz]icr (clock rate)
50 kBps 24 MHz 0x27
50 kBps 12 MHz 0x1f
50 kBps 6 MHz 0x17 or 0x1b
100 kBps 24 MHz 0x1f
100 kBps 12 MHz 0x17 or 0x1b
100 kBps 6 MHz 0x0e or 0x11 or 0x12
200 kBps 24 MHz 0x17 or 0x1b
200 kBps 12 MHz 0x0e or 0x11 or 0x12
200 kBps 6 MHz 0x05
400 kBps 24 MHz 0x0e or 0x11 or 0x12
400 kBps 12 MHz 0x05
#define I2C_MODULE_IRQ_EN_CONFIG (   icr)
Value:
(tI2C){ \
/* A1 */ CLR(I2C_A1_AD(0)), \
/* F */ SET(I2C_F_MULT(0))|SET(I2C_F_ICR(icr)), \
/* C1 */ SET(I2C_C1_IICEN_MASK)|SET(I2C_C1_IICIE_MASK)| \
/* .... */ CLR(I2C_C1_MST_MASK)|CLR(I2C_C1_TX_MASK)| \
/* .... */ CLR(I2C_C1_TXAK_MASK)|CLR(I2C_C1_RSTA_MASK)| \
/* .... */ CLR(I2C_C1_WUEN_MASK)|CLR(I2C_C1_DMAEN_MASK), \
/* C2 */ CLR(I2C_C2_GCAEN_MASK)|CLR(I2C_C2_ADEXT_MASK)| \
/* .... */ CLR(I2C_C2_HDRS_MASK)|CLR(I2C_C2_SBRC_MASK)| \
/* .... */ CLR(I2C_C2_RMEN_MASK)|CLR(I2C_C2_AD(0)), \
/* FLT */ CLR(I2C_FLT_FLT(0)), \
/* RA */ CLR(I2C_RA_RAD(0)), \
/* SMB */ CLR(I2C_SMB_FACK_MASK)|CLR(I2C_SMB_ALERTEN_MASK)| \
/* .... */ CLR(I2C_SMB_SIICAEN_MASK)|CLR(I2C_SMB_TCKSEL_MASK)| \
/* .... */ CLR(I2C_SMB_SLTF_MASK)|CLR(I2C_SMB_SHTF2_MASK)| \
/* .... */ CLR(I2C_SMB_SHTF2IE_MASK), \
/* A2 */ CLR(I2C_A2_SAD(0)), \
/* SLTH */ CLR(I2C_SLTH_SSLT(0)), \
/* SLTL */ CLR(I2C_SLTL_SSLT(0)) \
}

Module is enabled after initialization, master mode, IRQ enabled.\

Parameters
icrclock rate (see also "I2C divider and hold values" table in RD).
Note
I2C baud rates selector:
Baud rate [kBps]Bus clock [MHz]icr (clock rate)
50 kBps 24 MHz 0x27
50 kBps 12 MHz 0x1f
50 kBps 6 MHz 0x17 or 0x1b
100 kBps 24 MHz 0x1f
100 kBps 12 MHz 0x17 or 0x1b
100 kBps 6 MHz 0x0e or 0x11 or 0x12
200 kBps 24 MHz 0x17 or 0x1b
200 kBps 12 MHz 0x0e or 0x11 or 0x12
200 kBps 6 MHz 0x05
400 kBps 24 MHz 0x0e or 0x11 or 0x12
400 kBps 12 MHz 0x05