MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
ADC Operation from Internal 1.0 V PMC Bandgap VREF

This example shows typical use of the Analog-to-Digital Converter (ADC) in 16-bit, software triggered single and polled conversion mode with internal 1.0V PMC bandgap voltage reference. The ADC module is clocked by 2.4 MHz ADC asynchronous clock source (ADLPC=1, ADHSC=0). The device enters into Very Low Power (VLPR) mode after main blocks such PMC, SIM and SMC modules are initialized. The ADC measures analogue voltage on the AD10 input channel - on the TWR-KM34Z75M board, the AD10 input channel is connected to a 5K potentiometer (R20).

The FreeMASTER communicates via UART2 that is configured for 38400/8-N-1 and serviced by the application software in a polling mode. When using TWR-KM34Z75M board, connect USB port of your PC to the on-board OpenSDA's USB to serial bridge (J27). The following FreeMASTER screenshot demonstrates time waveform of the ad10_value variable, which reflects voltage changes on the AD10 input channel.

adc_bgap.bmp
Source code:
/******************************************************************************
* (c) Copyright 2010-2015, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
******************************************************************************
* adcbgap_test.c
******************************************************************************/
#include "drivers.h"
static volatile uint16 ad10_value;
void main (void)
{
/* enable PMC buffer operation also in VLPx modes and bandgap buffer in */
/* low power mode */
/* SMC and SIM modules */
/* switch to VLPR mode */
SMC_SetMode(VLPR);
/* ADC module */
ADC_Init (ADC_MODULE_16B_SWTRG_BGAP_LP_INTERNAL_CLK_CONFIG,
(ADC_CALLBACK)NULL);
/* initialize UART and FreeMASTER */
FMSTR_Init();
while (1)
{
FMSTR_Poll ();
if (ADC_Ready(CHA))
{
ad10_value = ADC_Read(CHA);
}
}
}
Appconfig.h:
/******************************************************************************
* (c) Copyright 2010, Freescale Semiconductor Inc.
* ALL RIGHTS RESERVED.
***************************************************************************/
#ifndef __APPCONFIG_H
#define __APPCONFIG_H
/***************************************************************************/
//#define MTB_RAM_RESERVE
/***************************************************************************/
#define BOOT_NMI_DISABLE
/***************************************************************************/
#define ADC_MODULE_16B_SWTRG_BGAP_LP_INTERNAL_CLK_CONFIG \
(tADC){ \
/* CFG1 */ SET(ADC_CFG1_ADLPC_MASK)|SET(ADC_CFG1_ADIV(0))| \
CLR(ADC_CFG1_ADLSMP_MASK)|SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(3)), \
/* CFG2 */ CLR(ADC_CFG2_MUXSEL_MASK)|SET(ADC_CFG2_ADACKEN_MASK)| \
CLR(ADC_CFG2_ADHSC_MASK)|SET(ADC_CFG2_ADLSTS(3)), \
/* CV1 */ 0l, \
/* CV2 */ 0l, \
/* SC2 */ CLR(ADC_SC2_ADTRG_MASK)|CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|SET(ADC_SC2_REFSEL(2)), \
/* SC3 */ CLR(ADC_SC3_CAL_MASK)|CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|SET(ADC_SC3_AVGS(0)), \
}
/******************************************************************************/
#endif /* __APPCONFIG_ */
Freemaster_cfg.h:
/***************************************************************************/
#ifndef __FREEMASTER_CFG_H
#define __FREEMASTER_CFG_H
/******************************************************************************
* Select interrupt or poll-driven serial communication
*******************************************************************************/
#define FMSTR_LONG_INTR 0 /* complete msg processing in interrupt */
#define FMSTR_SHORT_INTR 0 /* SCI FIFO-queuing done in interrupt */
#define FMSTR_POLL_DRIVEN 1 /* no interrupt needed, polling only */
/******************************************************************************
* Select SCI communication interface
*******************************************************************************/
#define FMSTR_USE_SCI 1 /* To select SCI communication interface */
#define FMSTR_USE_PDBDM 0 /* To select Packet Driven BDM interface */
//#define FMSTR_SCI_BASE 0x4006A000 /* UART0 base on MKM34Z50 */
#define FMSTR_SCI_BASE 0x4006B000 /* UART1 base on MKM34Z50 */
//#define FMSTR_SCI_BASE 0x4006C000 /* UART2 base on MKM34Z50 */
//#define FMSTR_SCI_BASE 0x4006D000 /* UART3 base on MKM34Z50 */
//
/******************************************************************************
* Input/output communication buffer size
*******************************************************************************/
#define FMSTR_COMM_BUFFER_SIZE 200 /* set to 0 for "automatic" */
/******************************************************************************
* Receive FIFO queue size (use with FMSTR_SHORT_INTR only)
*******************************************************************************/
#define FMSTR_COMM_RQUEUE_SIZE 32 /* set to 0 for "default" */
/******************************************************************************
* Support for Application Commands
*******************************************************************************/
#define FMSTR_USE_APPCMD 0 /* enable/disable App.Commands support */
#define FMSTR_APPCMD_BUFF_SIZE 32 /* App.Command data buffer size */
#define FMSTR_MAX_APPCMD_CALLS 4 /* num. of app.cmd callbacks? (0=disable) */
/******************************************************************************
* Oscilloscope support
*******************************************************************************/
#define FMSTR_USE_SCOPE 1 /* enable/disable scope support */
#define FMSTR_MAX_SCOPE_VARS 8 /* max. number of scope variables (2..8) */
/******************************************************************************
* Recorder support
*******************************************************************************/
#define FMSTR_USE_RECORDER 1 /* enable/disable recorder support */
#define FMSTR_MAX_REC_VARS 8 /* max. num. of recorder variables (2..8) */
/* built-in recorder buffer (use when FMSTR_REC_OWNBUFF is 0) */
#define FMSTR_REC_BUFF_SIZE 4096 /* built-in buffer size */
/* recorder time base, specifies how often the recorder is called */
#define FMSTR_REC_TIMEBASE FMSTR_REC_BASE_MILLISEC(0) /* 0 = "unknown" */
#define FMSTR_REC_FLOAT_TRIG 0 /* enable/disable floating point trigger */
/******************************************************************************
* Target-side address translation (TSA)
*******************************************************************************/
#define FMSTR_USE_TSA 0 /* enable TSA functionality */
#define FMSTR_USE_TSA_SAFETY 0 /* enable access to TSA variables only */
#define FMSTR_USE_TSA_INROM 0 /* TSA tables as const (put to ROM) */
/******************************************************************************
* Enable the byte access to communication buffer. All Cortex M0-based devices
* require this option to be set in order to avoid misaligned access to integer
* parameters which is unsupported on this platform.
*******************************************************************************/
#define FMSTR_BYTE_BUFFER_ACCESS 1
#endif /* __FREEMASTER_CFG_H */
Toolchain support:
IAR EWARM 7.40.7CodeWarrior 10.6KEIL uVision 5.15CrossWorks 3.6ATOLLIC TrueStudio 5.3.0Kinetis Design Studio 3.0.0