MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
LPUART Configuration Structures

Overview

This section describes default configuration structures for UART module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define LPUART_MODULE_POLLMODE_CONFIG(brate, clk)
 Configures LPUART to operate in polling mode. Receive and transmit data is not inverted. More...
 
#define LPUART_MODULE_POLLMODE_TXINV_CONFIG(brate, clk)
 Configures LPUART to operate in polling mode. Receive data is not inverted. Transmit data is inverted. More...
 
#define LPUART_MODULE_INTRMODE_CONFIG(brate, clk)
 Configures LPUART to operate in interrupt mode. Receive and transmit data is not inverted. More...
 
#define LPUART_MODULE_INTRMODE_TXINV_CONFIG(brate, clk)
 Configures LPUART to operate in interrupt mode. Receive data is not inverted. Transmit data is inverted. More...
 
#define LPUART_MODULE_RDRF_DMA_CONFIG(brate, clk)
 Configures LPUART to operate in receive DMA mode. Receive data register full flag will cause DMA request. More...
 
#define LPUART_MODULE_TDRE_DMA_CONFIG(brate, clk)
 Configures LPUART to operate in transmit DMA mode. Transmit data register empty flag will cause DMA request. More...
 
#define LPUART_MODULE_RDRF_TDRE_DMA_CONFIG(brate, clk)
 Configures LPUART to operate in DMA mode. Receive data register full flag and transmit data register empty will cause DMA requests. More...
 

Macro Definition Documentation

#define LPUART_MODULE_POLLMODE_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ CLR(LPUART_BAUD_TDMAE_MASK)|CLR(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|CLR(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in polling mode. Receive and transmit data is not inverted.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_POLLMODE_TXINV_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ CLR(LPUART_BAUD_TDMAE_MASK)|CLR(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|SET(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in polling mode. Receive data is not inverted. Transmit data is inverted.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_INTRMODE_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ CLR(LPUART_BAUD_TDMAE_MASK)|CLR(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|CLR(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in interrupt mode. Receive and transmit data is not inverted.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_INTRMODE_TXINV_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ CLR(LPUART_BAUD_TDMAE_MASK)|CLR(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|SET(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in interrupt mode. Receive data is not inverted. Transmit data is inverted.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_RDRF_DMA_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ CLR(LPUART_BAUD_TDMAE_MASK)|SET(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|CLR(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in receive DMA mode. Receive data register full flag will cause DMA request.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_TDRE_DMA_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ SET(LPUART_BAUD_TDMAE_MASK)|CLR(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|CLR(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in transmit DMA mode. Transmit data register empty flag will cause DMA request.

Parameters
brateBaud rate.
clkModule clock in Hz.
#define LPUART_MODULE_RDRF_TDRE_DMA_CONFIG (   brate,
  clk 
)
Value:
(tLPUART){ \
/* BAUD */ CLR(LPUART_BAUD_MAEN1_MASK)|CLR(LPUART_BAUD_MAEN2_MASK)| \
/* ..... */ CLR(LPUART_BAUD_M10_MASK)|((15<<24)&0x1f000000)| \
/* ..... */ SET(LPUART_BAUD_TDMAE_MASK)|SET(LPUART_BAUD_RDMAE_MASK)| \
/* ..... */ SET(LPUART_BAUD_MATCFG(0x0))|CLR(LPUART_BAUD_BOTHEDGE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RESYNCDIS_MASK)|CLR(LPUART_BAUD_LBKDIE_MASK)| \
/* ..... */ CLR(LPUART_BAUD_RXEDGIE_MASK)|CLR(LPUART_BAUD_SBNS_MASK)| \
/* ..... */ (LPUART_CALC_SBR(brate,clk)&0x1FFF), \
/* STAT */ CLR(LPUART_STAT_MSBF_MASK)|CLR(LPUART_STAT_RXINV_MASK)| \
/* ..... */ CLR(LPUART_STAT_RWUID_MASK)|CLR(LPUART_STAT_BRK13_MASK)| \
/* ..... */ CLR(LPUART_STAT_LBKDE_MASK), \
/* CTRL */ CLR(LPUART_CTRL_R8T9_MASK)|CLR(LPUART_CTRL_R9T8_MASK)| \
/* ..... */ CLR(LPUART_CTRL_TXDIR_MASK)|CLR(LPUART_CTRL_TXINV_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ORIE_MASK)|CLR(LPUART_CTRL_NEIE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_FEIE_MASK)|CLR(LPUART_CTRL_PEIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TIE_MASK)|CLR(LPUART_CTRL_TCIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_RIE_MASK)|CLR(LPUART_CTRL_ILIE_MASK)| \
/* ..... */ SET(LPUART_CTRL_TE_MASK)|SET(LPUART_CTRL_RE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_RWU_MASK)|CLR(LPUART_CTRL_SBK_MASK)| \
/* ..... */ CLR(LPUART_CTRL_MA1IE_MASK)|CLR(LPUART_CTRL_MA2IE_MASK)| \
/* ..... */ SET(LPUART_CTRL_IDLECFG(0x0))|CLR(LPUART_CTRL_LOOPS_MASK)| \
/* ..... */ CLR(LPUART_CTRL_DOZEEN_MASK)|CLR(LPUART_CTRL_RSRC_MASK)| \
/* ..... */ CLR(LPUART_CTRL_M_MASK)|CLR(LPUART_CTRL_WAKE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_ILT_MASK)|CLR(LPUART_CTRL_PE_MASK)| \
/* ..... */ CLR(LPUART_CTRL_PT_MASK), \
/* MATCH */ SET(LPUART_MATCH_MA2(0x0))|SET(LPUART_MATCH_MA1(0x0)) \
}

Configures LPUART to operate in DMA mode. Receive data register full flag and transmit data register empty will cause DMA requests.

Parameters
brateBaud rate.
clkModule clock in Hz.