This section describes default configuration structures for AFE module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define AFE_MODULE_RJFORMAT_CONFIG |
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src, |
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div, |
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freq |
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Value:(tAFE){ \
SET(AFE_CR_MSTR_EN_MASK)|
CLR(AFE_CR_SOFT_TRG0_MASK)| \
CLR(AFE_CR_SOFT_TRG1_MASK)|
CLR(AFE_CR_SOFT_TRG2_MASK)| \
CLR(AFE_CR_SOFT_TRG3_MASK)|
CLR(AFE_CR_LPM_EN_MASK)| \
SET(AFE_CR_RST_B_MASK)|
SET(AFE_CR_DLY_OK_MASK)| \
SET(AFE_CR_RESULT_FORMAT_MASK)| \
SET(AFE_CR_STRTUP_CNT((
uint8)((freq/(1<<div))*20e-6))), \
AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}
Selects normal mode of operation with right justified 2's complement 32-bit output data format.
- Parameters
-
src | Select one of the AFE Clock Sources. |
div | Select one of the AFE Clock Dividers. |
freq | Clock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field. |
#define AFE_MODULE_LJFORMAT_CONFIG |
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src, |
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div, |
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freq |
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) |
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Value:(tAFE){ \
SET(AFE_CR_MSTR_EN_MASK)|
CLR(AFE_CR_SOFT_TRG0_MASK)| \
CLR(AFE_CR_SOFT_TRG1_MASK)|
CLR(AFE_CR_SOFT_TRG2_MASK)| \
CLR(AFE_CR_SOFT_TRG3_MASK)|
CLR(AFE_CR_LPM_EN_MASK)| \
SET(AFE_CR_RST_B_MASK)|
SET(AFE_CR_DLY_OK_MASK)| \
CLR(AFE_CR_RESULT_FORMAT_MASK)| \
SET(AFE_CR_STRTUP_CNT((
uint8)((freq/(1<<div))*20e-6))), \
AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}
Selects normal mode of operation with left justified 2's complement 32-bit output data format.
- Parameters
-
src | Select one of the AFE Clock Sources. |
div | Select one of the AFE Clock Dividers. |
freq | Clock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field. |
#define AFE_MODULE_LPM_RJFORMAT_CONFIG |
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src, |
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div, |
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freq |
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) |
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Value:(tAFE){ \
SET(AFE_CR_MSTR_EN_MASK)|
CLR(AFE_CR_SOFT_TRG0_MASK)| \
CLR(AFE_CR_SOFT_TRG1_MASK)|
CLR(AFE_CR_SOFT_TRG2_MASK)| \
CLR(AFE_CR_SOFT_TRG3_MASK)|
SET(AFE_CR_LPM_EN_MASK)| \
SET(AFE_CR_RST_B_MASK)|
SET(AFE_CR_DLY_OK_MASK)| \
SET(AFE_CR_RESULT_FORMAT_MASK)| \
SET(AFE_CR_STRTUP_CNT((
uint8)((freq/(1<<div))*20e-6))), \
AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}
Selects low power mode of operation with right justified 2's complement 32-bit output data format.
- Parameters
-
src | Select one of the AFE Clock Sources. |
div | Select one of the AFE Clock Dividers. |
freq | Clock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field. |
#define AFE_MODULE_LPM_LJFORMAT_CONFIG |
( |
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src, |
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div, |
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freq |
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) |
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Value:(tAFE){ \
SET(AFE_CR_MSTR_EN_MASK)|
CLR(AFE_CR_SOFT_TRG0_MASK)| \
CLR(AFE_CR_SOFT_TRG1_MASK)|
CLR(AFE_CR_SOFT_TRG2_MASK)| \
CLR(AFE_CR_SOFT_TRG3_MASK)|
SET(AFE_CR_LPM_EN_MASK)| \
SET(AFE_CR_RST_B_MASK)|
SET(AFE_CR_DLY_OK_MASK)| \
CLR(AFE_CR_RESULT_FORMAT_MASK)| \
SET(AFE_CR_STRTUP_CNT((
uint8)((freq/(1<<div))*20e-6))), \
AFE_CKR_DIV(div)|AFE_CKR_CLS(src), \
}
Selects low power mode of operation with left justified 2's complement 32-bit output data format.
- Parameters
-
src | Select one of the AFE Clock Sources. |
div | Select one of the AFE Clock Dividers. |
freq | Clock frequency in Hz (e.g. 12288000); this value is used by the precompiler to calculate value for the AFE_CR_STRTUP_CNT register field. |