MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
AFE API Specification

Overview

This section describes functions and macros of the driver's API.

Macros

#define AFE_SelClkDiv(div)
 Selects AFE clock divider value. More...
 
#define AFE_SelClk(src)
 Selects AFE clock source. More...
 
#define AFE_SwTrigger(mask)
 Triggers conversion on selected AFE channel(s). More...
 
#define AFE_EnableDMA(mask)
 Enables DMA conversion on selected AFE channel(s). More...
 
#define AFE_SwReset()
 Resets SD ADC, PGA and Decimator filters. More...
 
#define AFE_DlyOk()
 Asserts DLY_OK bit. More...
 
#define AFE_DlyWrite(ch, dly)
 Writes new phase delay value to the selected AFE channel. More...
 
#define AFE_DlyUpdate(dly0, dly1, dly2, dly3)
 Updates all AFE channels with new delay values. More...
 
#define AFE_GainCtrl(ch, gain)
 Controls PGA gain stage for given channels. More...
 
#define AFE_ChReady(ch)
 Returns conversion status (COCx flag) for given AFE channel. More...
 
#define AFE_ChOverflow(ch)
 Returns overflow status (OVRx flag) for given AFE channel. More...
 
#define AFE_ChRead(ch)
 Returns 2's complement 32-bit value of the selected channel result register. More...
 
#define AFE_Read(mask, ptr)
 Returns 2's complement 32-bit values of the selected channel result registers. More...
 
#define AFE_Disable()
 Disables AFE operation. More...
 
#define AFE_ChInit(ch, cfg, dly, ip, callback)
 AFE channel initialization. More...
 
#define AFE_Init(cfg)
 AFE module initialization. More...
 

Macro Definition Documentation

#define AFE_SelClkDiv (   div)

This macro selects AFE clock divider value.

Parameters
divSelect one of the AFE Clock Dividers
Note
Implemented as an inline macro.
#define AFE_SelClk (   src)

This macro selects AFE clock source.

Parameters
srcSelect one of the AFE Clock Sources
Note
Implemented as an inline macro.
#define AFE_SwTrigger (   mask)

This macro triggers conversion by software on AFE channels selected by the channel mask.

Parameters
maskSelect one or more OR'ed Generic Peripheral Channels.
Note
Implemented as an inline macro.
Warning
Once the trigger capture logic receives a trigger it will ignore input trigger for next 2 mod_clk cycles. If some trigger comes in between it will be ignored. If triggers are more than 2 mod_clk cycles apart then it will cause re-sync operation. This is valid for both hardware and software trigger.
#define AFE_EnableDMA (   mask)

This macro enables DMA conversion on selected AFE channels selected by the channel mask.

Parameters
maskSelect one or more OR'ed Generic Peripheral Channels.
Note
Implemented as an inline macro.
#define AFE_SwReset ( )

This macro resets SD ADC, PGA and Decimator filters. It also de-asserts any pending interrupts. When called any internal state machine will come to its reset state.

Note
Implemented as an inline macro.
#define AFE_DlyOk ( )

This macro asserts DLY_OK bit so written phase delay values on all AFE channel will become active when a new conversion starts.

Note
Implemented as an inline macro.
#define AFE_DlyWrite (   ch,
  dly 
)

This macro writes new phase delay value to the selected AFE channel. The new phase delay value will become active after AFE_DlyOk() macro is called and a new conversion starts. Since channel phase delay can only increase the zero value is written to delay register instead of negative phase delay value.

Parameters
chCH0,CH1,CH2,CH3.
dlyChannel phase delay (signed integer value -2047 to 2047).
Note
Implemented as an inline macro.
See also
AFE_DlyOk
#define AFE_DlyUpdate (   dly0,
  dly1,
  dly2,
  dly3 
)

This macro updates all AFE channels with new delay values provided as the input arguments of this macro. The macro also sets DLY_OK bit so all new delay values will become active after new conversion. Since channel phase delay can only increase the zero values are written to delay registers instead of any negative phase delay values.

Parameters
dly0Channel 0 phase delay (signed integer value -2047 to 2047).
dly1Channel 1 phase delay (signed integer value -2047 to 2047).
dly2Channel 2 phase delay (signed integer value -2047 to 2047).
dly3Channel 3 phase delay (signed integer value -2047 to 2047).
Note
Implemented as an inline macro.
See also
AFE_DlyWrite
#define AFE_GainCtrl (   ch,
  gain 
)

This macro controls PGA gain stage for channels with built-in Programmable Gain Amplifier (PGA).

Parameters
chCH0,CH1,CH2,CH3.
gainSelect one of the AFE PGA Gain Stages. Note that PGA_DISABLE argument disables PGA completely.
Note
Implemented as an inline macro.
#define AFE_ChReady (   ch)

This macro returns conversion status (COCx flag) for given AFE channel.

Parameters
chCH0,CH1,CH2,CH3.
Returns
true (non-zero) conversion completed (COC flag is asserted),
false conversion pending (COC flag is deasserted).
Note
Implemented as an inline macro.
See also
AFE_ChRead, AFE_Read, AFE_ChOverflow
#define AFE_ChOverflow (   ch)

This macro returns overflow status (OVRx flag) for given AFE channel.

Parameters
chCH0,CH1,CH2,CH3.
Returns
true (non-zero) data overwritten (OVR flag is asserted),
false data not overwritten (OVR flag is deasserted).
Note
Implemented as an inline macro.
See also
AFE_ChRead, AFE_Read, AFE_ChReady
#define AFE_ChRead (   ch)

This macro returns 2's complement 32-bit value of the selected channel result register. The alignment of the data format is either left or right justified based on the configuration structure AFE Module Configuration Structures passed to the AFE_Init() initialization function.

Parameters
chCH0,CH1,CH2,CH3.
Returns
int32 2's complement result register value.
Note
Implemented as an inline macro.
See also
AFE_ChReady, AFE_ChOverflow
#define AFE_Read (   mask,
  ptr 
)

This macro returns 2's complement 32-bit value of the selected channel result registers. The alignment of the data format is either left or right justified based on the configuration structure AFE Module Configuration Structures passed to the AFE_Init() initialization function.

Parameters
maskSelect one or more OR'ed Generic Peripheral Channels.
ptrPointer to the int32 array of the size that equals to number of channels processed by the function. The values of lower channels are stored first.
Note
Implemented as an inline macro.
See also
AFE_ChReady, AFE_ChOverflow
#define AFE_Disable ( )

This macro disables AFE operation. It also disables interrupts, DMA transfers and initializes control registers.

Note
Implemented as an inline macro. Call this macro to disable AFE operation prior changing its configuration.
See also
AFE_Init, AFE_ChInit
#define AFE_ChInit (   ch,
  cfg,
  dly,
  ip,
  callback 
)

This function initializes channel of the Analogue Front End (AFE) selected by the input argument. It also installs callback function for interrupt vectors associated with initialized AFE channels: vector 37(CH0), vector 38(CH1), vector 39(CH2) and vector 40(CH3).

Parameters
chCH0,CH1,CH2,CH3.
cfgSelect one of the AFE Channel Configuration Structures.
dlyChannel phase delay (signed integer value -2047 to 2047). Since channel phase delay can only increases the zero value is written to the delay register instead of any negative phase delay value.
ipSelect one of the ARM Cortex-M0+ Interrupt Priority Levels.
callbackPointer to the AFE Callback Function
Note
Implemented as a function call.
See also
AFE_Init
#define AFE_Init (   cfg)

This function initializes Analogue Front End (AFE) module. The function can also trigger conversions by software on the respective channels provided those channels have been already initialized using AFE_ChInit function call.

Parameters
cfgSelect one of the AFE Module Configuration Structures.
Note
Implemented as a function call.
See also
AFE_ChInit, AFE_Disable