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MKMxxZxxACxx5 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes default configuration structures for DMA channel configuration. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
Macros | |
#define | DMA_CH_SWTRG_M2M_CN_CONFIG(srcaddr, dstaddr, nbytes) |
Selects and starts software triggered continuous memory to memory data transfer. More... | |
#define | DMA_CH_SWTRG_M2P_CN_CONFIG(srcaddr, regsize, regaddr, nbytes) |
Selects software initiated continuous memory to peripheral data transfer. More... | |
#define | DMA_CH_HWTRG_M2M_CN_CONFIG(reqsrc, regsize, srcaddr, dstaddr, nbytes) |
Selects and starts hardware triggered continuous memory to memory data transfer. More... | |
#define | DMA_CH_HWTRG_M2M_CS_CONFIG(reqsrc, regsize, srcaddr, dstaddr, nbytes) |
Selects and starts hardware triggered cycle steal memory to memory data transfer. More... | |
#define | DMA_CH_HWTRG_P2M_CS_CONFIG(reqsrc, regsize, regaddr, dstaddr, nbytes) |
Selects hardware initiated cycle steal peripheral to memory data transfer. More... | |
#define | DMA_CH_HWTRG_M2P_CS_CONFIG(reqsrc, srcaddr, regsize, regaddr, nbytes) |
Selects hardware initiated cycle steal memory to peripheral data transfer. More... | |
#define | DMA_CH_HWTRG_P2P_CS_LOOP_CONFIG(reqsrc, regsize, reg1addr, reg2addr, nbytes) |
Selects hardware initiated cycle steal peripheral to peripheral data transfer executed in a loop. More... | |
#define DMA_CH_SWTRG_M2M_CN_CONFIG | ( | srcaddr, | |
dstaddr, | |||
nbytes | |||
) |
Configures and starts DMA channel to operate in software trigger continuous memory to memory data transfer.
srcaddr | Source memory buffer address (uint32). |
dstaddr | Destination memory buffer address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_SWTRG_M2P_CN_CONFIG | ( | srcaddr, | |
regsize, | |||
regaddr, | |||
nbytes | |||
) |
Configures software initiated continuous memory to peripheral data transfer.
srcaddr | Source memory buffer address (uint32-regsize aligned) |
regsize | Select DMA Transfer Sizes. |
regaddr | Destination peripheral register address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_HWTRG_M2M_CN_CONFIG | ( | reqsrc, | |
regsize, | |||
srcaddr, | |||
dstaddr, | |||
nbytes | |||
) |
Configures and starts DMA channel to operate in hardware trigger continuous memory to memory data transfer.
reqsrc | Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources. |
regsize | Select DMA Transfer Sizes. |
srcaddr | Source memory buffer address (uint32). |
dstaddr | Destination memory buffer address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_HWTRG_M2M_CS_CONFIG | ( | reqsrc, | |
regsize, | |||
srcaddr, | |||
dstaddr, | |||
nbytes | |||
) |
Configures and starts DMA channel to operate in hardware trigger cycle steal memory to memory data transfer.
reqsrc | Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources. |
regsize | Select DMA Transfer Sizes. |
srcaddr | Source memory buffer address (uint32). |
dstaddr | Destination memory buffer address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_HWTRG_P2M_CS_CONFIG | ( | reqsrc, | |
regsize, | |||
regaddr, | |||
dstaddr, | |||
nbytes | |||
) |
Configures hardware initiated cycle steal peripheral to memory data transfer.
reqsrc | Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources. |
regsize | Select DMA Transfer Sizes. |
regaddr | Peripheral register address (uint32). |
dstaddr | Destination memory buffer address (uint32-regsize aligned). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_HWTRG_M2P_CS_CONFIG | ( | reqsrc, | |
srcaddr, | |||
regsize, | |||
regaddr, | |||
nbytes | |||
) |
Configures hardware initiated cycle steal memory to peripheral data transfer.
reqsrc | Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources. |
srcaddr | Source memory buffer address (uint32-regsize aligned) |
regsize | Select DMA Transfer Sizes. |
regaddr | Destination peripheral register address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |
#define DMA_CH_HWTRG_P2P_CS_LOOP_CONFIG | ( | reqsrc, | |
regsize, | |||
reg1addr, | |||
reg2addr, | |||
nbytes | |||
) |
Configures hardware initiated cycle steal peripheral to peripheral data transfer executed in a loop.
reqsrc | Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources. |
regsize | Select DMA Transfer Sizes. |
reg1addr | Source peripheral register address (uint32). |
reg2addr | Destination peripheral register address (uint32). |
nbytes | Bytes count to be transferred in range 0x000001 to 0x0FFFFF. |