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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This example shows typical use of the Phase Delay Block (PDB) back to back trigger function in software trigger mode. The PDB module is initially clocked by a BUSCLK. The BUSCLK is 1MHz in this case. PDB counter modulo is configured on 60000 count (the counter overflows after about 60ms). Pre-trigger channel is configured in the delayed mode and channels 2 and 3 are configured in the back to back mode with bypassed delay. Pre-trigger CH0 triggers ADC's CHA (this channel measures ADC single input 8) after a 5ms delay after the PDB SW counter trigger. Conversion complete signal of ADC's CHA is routed to the acknowledgement of PDB's pre-trigger CH1. Pre-trigger CH1 triggers ADC's CHB (this channel measures ADC single input 15.) Conversion complete signal of ADC's CHB is routed to the acknowledgement of PDB's pre-trigger CH2. PDB's Pre-trigger channels are triggered immediately after the conversion complete signal is asserted. When the PDB counter reaches 60000 counts the counter overflows and whole process is repeating.
IAR EWARM 7.40.7 | KEIL uVision 5.15 | CrossWorks 3.6 | ATOLLIC TrueStudio 5.3.0 | Kinetis Design Studio 3.0.0 |
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