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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This example shows typical use of the Programmable Delay Block (PDB) ADC trigger function in software trigger mode. The PDB module is initially clocked with a BUSCLK. The BUSCLK is 1MHz in this case. PDB counter modulo is configured on 60000 count (after about 60ms the counter overflows). Pre-trigger channels are configured in delayed mode. Pre-trigger CH0 triggers ADC's CHA (this channel measures ADC single input 8) after a 5ms delay after the PDB SW counter trigger. After next 10ms the pre-trigger CH1 triggers ADC's CHB (this channel measures ADC single input 15) and after next 10ms the pre-trigger CH2 triggers ADC's CHC (this channel measures ADC single input 14). When the PDB counter reaches 60000 counts the counter overflows and whole process is repeating.
IAR EWARM 7.40.7 | KEIL uVision 5.15 | CrossWorks 3.6 | ATOLLIC TrueStudio 5.3.0 | Kinetis Design Studio 3.0.0 |
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