MKMxxZxxACxx5 Bare Metal Software Drivers  R4.1.6
Reference Manual
Pin Assignments

Refer to PORT_Init function and respective PORT Configuration Structures.

100 QFP 64 QFP 44 LGA Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
1 1 - PTA0 DISABLED LCD23 PTA0 - - - - - -
2 2 - PTA1 DISABLED LCD24 PTA1 - - - - - -
3 3 - PTA2 DISABLED LCD25 PTA2 - - - - - -
4 - - PTA3 DISABLED LCD26 PTA3 - - - - - -
5 4 1 PTA4 NMI_B LCD27 PTA4 LLWU_P15 - - - - NMI_B
6 5 2 PTA5 DISABLED LCD28 PTA5 CMP0OUT - - - - -
7 6 3 PTA6 DISABLED LCD29 PTA6 PXBAR_IN0 LLWU_P14 - - - -
8 7 4 PTA7 DISABLED LCD30 PTA7 PXBAR_OUT0 - - - - -
9 - - PTB0 DISABLED LCD31 PTB0 - - - - - -
10 8 5 VDD VDD VDD - - - - - - -
11 9 6 VSS VSS VSS - - - - - - -
12 - - PTB1 DISABLED LCD32 PTB1 - - - - - -
13 - - PTB2 DISABLED LCD33 PTB2 - - - - - -
14 - - PTB3 DISABLED LCD34 PTB3 - - - - - -
15 - - PTB4 DISABLED LCD35 PTB4 - - - - - -
16 - - PTB5 DISABLED LCD36 PTB5 - - - - - -
17 - - PTB6 DISABLED LCD37/CMP1P0 PTB6 - - - - - -
18 10 - PTB7 DISABLED LCD38 PTB7 AFE_CLK - - - - -
19 11 - PTC0 DISABLED LCD39 PTC0 SCI3_RTS PXBAR_IN1 - - - -
20 12 - PTC1 DISABLED LCD40/CMP1P1 PTC1 SCI3_CTS - - - - -
21 13 - PTC2 DISABLED LCD41 PTC2 SCI3_TxD PXBAR_OUT1 - - - -
22 14 - PTC3 DISABLED LCD42/CMP0P3 PTC3 SCI3_RxD LLWU_P13 - - - -
23 - - PTC4 DISABLED LCD43 PTC4 - - - - - -
24 15 7 VBAT VBAT VBAT - - - - - - -
25 16 8 XTAL32K XTAL32K XTAL32K - - - - - - -
26 17 9 EXTAL32K EXTAL32K EXTAL32K - - - - - - -
27 18 10 VSS VSS VSS - - - - - - -
28 18 10 TAMPER2 TAMPER2 TAMPER2 - - - - - - -
29 18 10 TAMPER1 TAMPER1 TAMPER1 - - - - - - -
30 19 11 TAMPER0 TAMPER0 TAMPER0 - - - - - - -
31 20 12 VDDA VDDA VDDA - - - - - - -
32 21 13 VSSA VSSA VSSA - - - - - - -
33 22 14 SDADP0 SDADP0 SDADP0 - - - - - - -
34 23 15 SDADM0 SDADM0 SDADM0 - - - - - - -
35 24 16 SDADP1 SDADP1 SDADP1 - - - - - - -
36 25 17 SDADM1 SDADM1 SDADM1 - - - - - - -
37 26 18 VREFH VREFH VREFH - - - - - - -
38 27 19 VREFL VREFL VREFL - - - - - - -
39 28 20 SDADP2/CMP1P2 SDADP2/CMP1P2 SDADP2/CMP1P2 - - - - - - -
40 29 21 SDADM2/CMP1P3 SDADM2/CMP1P3 SDADM2/CMP1P3 - - - - - - -
41 30 22 VREF VREF VREF - - - - - - -
42 - 24 SDADP3/CMP1P4 SDADP3/CMP1P4 SDADP3/CMP1P4 - - - - - - -
43 - 23 SDADM3/CMP1P5 SDADM3/CMP1P5 SDADM3/CMP1P5 - - - - - - -
44 - - PTC5 DISABLED AD0 PTC5 SCI0_RTS LLWU_P12 - - - -
45 - - PTC6 DISABLED AD1 PTC6 SCI0_CTS QT1 - - - -
46 - - PTC7 DISABLED AD2 PTC7 SCI0_TxD PXBAR_OUT2 - - - -
47 - - PTD0 DISABLED CMP0P0 PTD0 SCI0_RxD PXBAR_IN2 LLWU_P11 - - -
48 31 - PTD1 DISABLED - PTD1 SCI1_TxD SPI0_SS_B PXBAR_OUT3 QT3 - -
49 32 - PTD2 DISABLED CMP0P1 PTD2 SCI1_RxD SPI0_SCK PXBAR_IN3 LLWU_P10 - -
50 33 - PTD3 DISABLED - PTD3 SCI1_CTS SPI0_MOSI - - - -
51 34 - PTD4 DISABLED AD3 PTD4 SCI1_RTS SPI0_MISO LLWU_P9 - - -
52 - - PTD5 DISABLED AD4 PTD5 LPTIM2 QT0 SCI3_CTS - - -
53 - - PTD6 DISABLED AD5 PTD6 LPTIM1 CMP1OUT SCI3_RTS LLWU_P8 - -
54 - - PTD7 DISABLED CMP0P4 PTD7 I2C0_SCL PXBAR_IN4 SCI3_RxD LLWU_P7 - -
55 - - PTE0 DISABLED - PTE0 I2C0_SDA PXBAR_OUT4 SCI3_TxD CLKOUT - -
56 35 25 PTE1 RESET_B - PTE1 - - - - - RESET_B
57 - 26 PTE2 EXTAL1 EXTAL1 PTE2 EWM_IN PXBAR_IN6 I2C1_SDA - - -
58 - 27 PTE3 XTAL1 XTAL1 PTE3 EWM_OUT AFE_CLK I2C1_SCL - - -
59 36 28 VSS VSS VSS - - - - - - -
60 36 29 SAR_VSSA SAR_VSSA SAR_VSSA - - - - - - -
61 37 30 SAR_VDDA SAR_VDDA SAR_VDDA - - - - - - -
62 37 31 VDD VDD VDD - - - - - - -
63 - - PTE4 DISABLED - PTE4 LPTIM0 SCI2_CTS EWM_IN - - -
64 - - PTE5 DISABLED - PTE5 QT3 SCI2_RTS EWM_OUT LLWU_P6 - -
65 38 32 PTE6 SWD_IO CMP0P2 PTE6 PXBAR_IN5 SCI2_RxD LLWU_P5 - - SWD_IO
66 39 33 PTE7 SWD_CLK AD6 PTE7 PXBAR_OUT5 SCI2_TxD - - - SWD_CLK
67 40 - PTF0 DISABLED AD7 PTF0 RTCCLKOUT QT2 CMP0OUT - - -
68 41 34 PTF1 DISABLED LCD0/AD8 PTF1 QT0 PXBAR_OUT6 - - - -
69 42 35 PTF2 DISABLED LCD1/AD9 PTF2 CMP1OUT RTCCLKOUT - - - -
70 43 - PTF3 DISABLED LCD2 PTF3 SPI1_SS_B LPTIM1 SCI0_RxD - - -
71 44 - PTF4 DISABLED LCD3 PTF4 SPI1_SCK LPTIM0 SCI0_TxD - - -
72 45 - PTF5 DISABLED LCD4 PTF5 SPI1_MISO I2C1_SCL LLWU_P4 - - -
73 46 - PTF6 DISABLED LCD5 PTF6 SPI1_MOSI I2C1_SDA LLWU_P3 - - -
74 47 - PTF7 DISABLED LCD6 PTF7 QT2 CLKOUT - - - -
75 48 - PTG0 DISABLED LCD7 PTG0 QT1 LPTIM2 - - - -
76 49 36 PTG1 DISABLED LCD8/AD10 PTG1 LLWU_P2 LPTIM0 - - - -
77 50 37 PTG2 DISABLED LCD9/AD11 PTG2 SPI0_SS_B LLWU_P1 - - - -
78 51 38 PTG3 DISABLED LCD10 PTG3 SPI0_SCK I2C0_SCL - - - -
79 52 39 PTG4 DISABLED LCD11 PTG4 SPI0_MOSI I2C0_SDA - - - -
80 53 40 PTG5 DISABLED LCD12 PTG5 SPI0_MISO LPTIM1 - - - -
81 54 - PTG6 DISABLED LCD13 PTG6 LLWU_P0 LPTIM2 - - - -
82 - - PTG7 DISABLED LCD14 PTG7 - - - - - -
83 - - PTH0 DISABLED LCD15 PTH0 - - - - - -
84 - - PTH1 DISABLED LCD16 PTH1 - - - - - -
85 - - PTH2 DISABLED LCD17 PTH2 - - - - - -
86 - - PTH3 DISABLED LCD18 PTH3 - - - - - -
87 - - PTH4 DISABLED LCD19 PTH4 - - - - - -
88 - - PTH5 DISABLED LCD20 PTH5 - - - - - -
89 - 41 PTH6 DISABLED - PTH6 SCI1_CTS SPI1_SS_B PXBAR_IN7 - - -
90 - 42 PTH7 DISABLED - PTH7 SCI1_RTS SPI1_SCK PXBAR_OUT7 - - -
91 55 43 PTI0 DISABLED CMP0P5 PTI0 SCI1_RxD PXBAR_IN8 SPI1_MISO SPI1_MOSI - -
92 56 44 PTI1 DISABLED - PTI1 SCI1_TxD PXBAR_OUT8 SPI1_MOSI SPI1_MISO - -
93 57 - PTI2 DISABLED LCD21 PTI2 - - - - - -
94 58 - PTI3 DISABLED LCD22 PTI3 - - - - - -
95 59 - VSS VSS VSS - - - - - - -
96 60 - VLL3 VLL3 VLL3 - - - - - - -
97 61 - VLL2 VLL2 VLL2 - - - - - - -
98 62 - VLL1 VLL1 VLL1 - - - - - - -
99 63 - VCAP2 VCAP2 VCAP2 - - - - - - -
100 64 - VCAP1 VCAP1 VCAP1 - - - - - - -

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