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MKM34Z256VLx7 Bare Metal Software Drivers
R4.1.6
Reference Manual
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This section describes default configuration structures for TMR module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
Macros | |
#define | TMR_CH_CNTR_DI_CONFIG1(prm_clk_src, sec_clk_src) |
Configures Timer/Counter Mode - Rollover. More... | |
#define | TMR_CH_CNTR_EN_CONFIG1(prm_clk_src, sec_clk_src) |
Enables Timer/Counter Mode - Rollover. More... | |
#define | TMR_CH_CNTR_DI_CONFIG2(prm_clk_src, sec_clk_src) |
Configures Timer/Counter Mode - One Shot. More... | |
#define | TMR_CH_CNTR_EN_CONFIG2(prm_clk_src, sec_clk_src) |
Enables Timer/Counter Mode - One Shot. More... | |
#define | TMR_CH_CNTR_DI_CONFIG3(prm_clk_src, sec_clk_src) |
Configures Simple Timer/Counter Mode. More... | |
#define | TMR_CH_CNTR_EN_CONFIG3(prm_clk_src, sec_clk_src) |
Enables Simple Timer/Counter Mode. More... | |
#define | TMR_CH_CNTR_DI_CONFIG4(prm_clk_src, sec_clk_src) |
Configures Simple Timer/Counter Mode. More... | |
#define | TMR_CH_CNTR_EN_CONFIG4(prm_clk_src, sec_clk_src) |
Enables Simple Timer/Counter Mode. More... | |
#define | TMR_CH_CAPT_DI_CONFIG1(prm_clk_src, sec_clk_src, input_mode) |
Configures Input Capture Mode. More... | |
#define | TMR_CH_CAPT_EN_CONFIG1(prm_clk_src, sec_clk_src, input_mode) |
Enables Input Capture Mode. More... | |
#define | TMR_CH_CAPT_DI_CONFIG2(prm_clk_src, sec_clk_src, input_mode) |
Configures Input Capture Mode. More... | |
#define | TMR_CH_CAPT_EN_CONFIG2(prm_clk_src, sec_clk_src, input_mode) |
Enables Input Capture Mode. More... | |
#define | TMR_CH_OUTCMP_DI_CONFIG(count_mode, prm_clk_src, sec_clk_src, output_mode) |
Configures Output Compare Mode. More... | |
#define | TMR_CH_OUTCMP_EN_CONFIG(count_mode, prm_clk_src, sec_clk_src, output_mode) |
Enables Output Compare Mode. More... | |
#define TMR_CH_CNTR_DI_CONFIG1 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Configures Timer/Counter Mode - Rollover. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The Timer is configured in Counter Mode with following the characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_EN_CONFIG1 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Enables Timer/Counter Mode - Rollover. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The Timer is configured in Counter Mode with following the characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_DI_CONFIG2 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Configures Timer/Counter Mode - One Shot. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_EN_CONFIG2 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Enables Timer/Counter Mode - One Shot. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_DI_CONFIG3 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Configures Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_EN_CONFIG3 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Enables Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_DI_CONFIG4 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Configures Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CNTR_EN_CONFIG4 | ( | prm_clk_src, | |
sec_clk_src | |||
) |
Enables Simple Timer/Counter Mode. Output mode is set to "Asserted while counter is active", Input Clock source selected is "Count Rising Edge of Primary Source". The timer is configured in Counter Mode with the following characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
#define TMR_CH_CAPT_DI_CONFIG1 | ( | prm_clk_src, | |
sec_clk_src, | |||
input_mode | |||
) |
Configures Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
input_mode | Select one of the TMR Input Capture Modes. |
#define TMR_CH_CAPT_EN_CONFIG1 | ( | prm_clk_src, | |
sec_clk_src, | |||
input_mode | |||
) |
Enables Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
input_mode | Select one of the TMR Input Capture Modes. |
#define TMR_CH_CAPT_DI_CONFIG2 | ( | prm_clk_src, | |
sec_clk_src, | |||
input_mode | |||
) |
Configures Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
input_mode | Select one of the TMR Input Capture Modes. |
#define TMR_CH_CAPT_EN_CONFIG2 | ( | prm_clk_src, | |
sec_clk_src, | |||
input_mode | |||
) |
Enables Input Capture Mode. The timer operates in Input Capture Mode. Default Primary Clock source rising edge is selected. Output mode is also fixed at "asserted while counter is active". Other characteristics:
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
input_mode | Select one of the TMR Input Capture Modes. |
#define TMR_CH_OUTCMP_DI_CONFIG | ( | count_mode, | |
prm_clk_src, | |||
sec_clk_src, | |||
output_mode | |||
) |
Configures Output Compare Mode. The timer operates in Output Compare Mode with the following characteristics:
count_mode | Select one of the TMR Count Modes. |
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
output_mode | Select one of the TMR OFLAG Signal Modes. |
#define TMR_CH_OUTCMP_EN_CONFIG | ( | count_mode, | |
prm_clk_src, | |||
sec_clk_src, | |||
output_mode | |||
) |
Enables Output Compare Mode. The timer operates in Output Compare Mode with the following characteristics:
count_mode | Select one of the TMR Count Modes. |
prm_clk_src | Select one of the TMR Primary Count Sources. |
sec_clk_src | Select one of the TMR Secondary Count Sources. |
output_mode | Select one of the TMR OFLAG Signal Modes. |