This section describes default configuration structures for PLL module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define PLL_MODULE_PEI_12MHZ_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x00))| \
SET(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x00))|
CLR(MCG_C2_HGO0_MASK)|\
CLR(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x01)), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged Internal. PLL clocked by 32 KHz Internal Reference Clock.
#define PLL_MODULE_PEE_12_288MHZ_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x00))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x00))|
CLR(MCG_C2_HGO0_MASK)|\
CLR(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x00)), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External. PLL clocked by 32 KHz RTC Oscillator Clock Source (32.768KHz external crystal).
#define PLL_MODULE_PEE_DIV32_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x00))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 - 14.64 MHz). Clocked by System Oscillator Clock with Frequency Range 1.0 - 1.25 MHz.
#define PLL_MODULE_PEE_DIV64_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x01))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 - 14.64 MHz). Clocked by System Oscillator Clock with Frequency Range 2.0 - 2.5 MHz.
#define PLL_MODULE_PEE_DIV128_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x02))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 - 14.64 MHz). Clocked by System Oscillator Clock with Frequency Range 4.0 - 5.0 MHz.
#define PLL_MODULE_PEE_DIV256_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x03))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 - 14.64 MHz). Clocked by System Oscillator Clock with Frequency Range 8.0 - 10.0 MHz.
#define PLL_MODULE_PEE_DIV512_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x04))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 - 14.64 MHz). Clocked by System Oscillator Clock with Frequency Range 16.0 - 20.0 MHz.
#define PLL_MODULE_PEE_DIV1024_OSC_CONFIG |
Value:(tPLL){ \
SET(MCG_C1_CLKS(0x00))|
SET(MCG_C1_FRDIV(0x05))| \
CLR(MCG_C1_IREFS_MASK)|
CLR(MCG_C1_IRCLKEN_MASK)| \
CLR(MCG_C1_IREFSTEN_MASK), \
SET(MCG_C2_LOCRE0_MASK)|
SET(MCG_C2_RANGE0(0x02))|
CLR(MCG_C2_HGO0_MASK)|\
SET(MCG_C2_EREFS0_MASK)|
CLR(MCG_C2_LP_MASK)|
CLR(MCG_C2_IRCS_MASK), \
SET(MCG_C5_PLLCLKEN0_MASK)|
SET(MCG_C5_PLLSTEN0_MASK), \
CLR(MCG_C6_LOLIE0_MASK)|
SET(MCG_C6_PLLS_MASK)|
CLR(MCG_C6_CME0_MASK)| \
SET(MCG_C6_CHGPMP_BIAS(0x08)), \
CLR(MCG_SC_ATME_MASK)|
CLR(MCG_SC_ATMS_MASK)| \
CLR(MCG_SC_FLTPRSRV_MASK)|
SET(MCG_SC_FCRDIV(0x00)), \
SET(MCG_C7_PLL32KREFSEL(0x02))|
CLR(MCG_C7_OSCSEL_MASK), \
SET(MCG_C8_LOCRE1_MASK)|
CLR(MCG_C8_LOLRE_MASK)|
CLR(MCG_C8_CME1_MASK)|\
CLR(MCG_C8_COARSE_LOLIE_MASK), \
}
PLL Engaged External (VCO Range: 11.71 MHz). Clocked by System Oscillator Clock with Frequency Range 32 MHz.