This section describes default configuration structures for ADC module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).
#define ADC_MODULE_16B_SWTRG_IREF_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
CLR(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
CLR(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(1)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit software triggered mode with internal voltage reference. It initializes ADC module to convert ADC Input Channels (MUXA).
#define ADC_MODULE_16B_SWTRG_XREF_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
CLR(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
CLR(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(0)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit software triggered mode with external voltage reference. It initializes ADC module to convert ADC Input Channels (MUXA).
#define ADC_MODULE_16B_HWTRG_IREF_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
CLR(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
SET(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(1)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit hardware triggered mode with internal voltage reference. It initializes ADC module to convert ADC Input Channels (MUXA).
#define ADC_MODULE_16B_HWTRG_XREF_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
CLR(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
SET(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(0)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit hardware triggered mode with external voltage reference. It initializes ADC module to convert ADC Input Channels (MUXA).
#define ADC_MODULE_16B_SWTRG_IREF_MUXB_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
SET(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
CLR(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(1)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit software triggered mode with internal voltage reference. It initializes ADC module to convert ADC Input Channels (MUXB).
#define ADC_MODULE_16B_SWTRG_XREF_MUXB_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
SET(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
CLR(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(0)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit software triggered mode with external voltage reference. It initializes ADC module to convert ADC Input Channels (MUXB).
#define ADC_MODULE_16B_HWTRG_IREF_MUXB_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
SET(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
SET(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(1)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit hardware triggered mode with internal voltage reference. It initializes ADC module to convert ADC Input Channels (MUXB).
#define ADC_MODULE_16B_HWTRG_XREF_MUXB_CONFIG |
Value:(tADC){ \
CLR(ADC_CFG1_ADLPC_MASK)|
SET(ADC_CFG1_ADIV(3))| \
SET(ADC_CFG1_ADLSMP_MASK)|
SET(ADC_CFG1_MODE(3))| \
SET(ADC_CFG1_ADICLK(0)), \
SET(ADC_CFG2_MUXSEL_MASK)|
CLR(ADC_CFG2_ADACKEN_MASK)| \
SET(ADC_CFG2_ADHSC_MASK)|
SET(ADC_CFG2_ADLSTS(0)), \
0l, \
0l, \
SET(ADC_SC2_ADTRG_MASK)|
CLR(ADC_SC2_ACFE_MASK)| \
CLR(ADC_SC2_ACFGT_MASK)|
CLR(ADC_SC2_ACREN_MASK)| \
CLR(ADC_SC2_DMAEN_MASK)|
SET(ADC_SC2_REFSEL(0)), \
CLR(ADC_SC3_CAL_MASK)|
CLR(ADC_SC3_ADCO_MASK)| \
CLR(ADC_SC3_AVGE_MASK)|
SET(ADC_SC3_AVGS(0)), \
}
Selects 16-bit hardware triggered mode with external voltage reference. It initializes ADC module to convert ADC Input Channels (MUXB).