MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
PLL API Specification

Overview

This section describes functions and macros of the driver's API.

Macros

#define PLL_Enable(clk)
 Selects PLL 32KHz reference clock and enables PLL module. More...
 
#define PLL_Disable()
 Macro disables PLL module. More...
 
#define PLL_CtrlPLLSTEN(x)
 Enable/disable PLL operation in normal Stop mode. More...
 
#define PLL_Init(cfg)
 PLL initialization. More...
 

Macro Definition Documentation

#define PLL_Enable (   clk)

This macro selects PLL 32KHz reference clock and enables PLL module. PLL is enabled by setting PLLCLKEN0 bit.

Parameters
clkSelect one of the PLL Reference Clock Sources.
Note
Implemented as an inline macro.
Warning
FLL or PLL is enabled by this macro (LP bit is deasserted). The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set.
See also
PLL_Disable, SIM_CtrlPLLVLP, PLL_CtrlPLLSTEN
#define PLL_Disable ( )

This macro disables PLL module by clearing MCG_C5[PLLCLKEN0] and setting MCG_C2[LP] bits.

Note
Implemented as an inline macro.
See also
PLL_Enable
#define PLL_CtrlPLLSTEN (   x)

This macro enables/disables PLL operation during normal stop mode by setting/clearing PLLSTEN0 bit, respectively.

Parameters
xTRUE (MCGPLLCLK is enabled if system is in normal Stop mode)
FALSE (MCGPLLCLK is disabled in any of the Stop modes).
Note
Implemented as an inline macro.
Warning
In Low Power Stop mode, the PLL clock gets disabled even if PLL operation was enabled using this macro. In all other power modes PLLSTEN0 bit has no affect and does not enable the PLL operation.
See also
PLL_Enable, PLL_Init, SIM_CtrlPLLVLP
#define PLL_Init (   cfg)

This function initializes Phase-Locked Loop (PLL).

Parameters
cfgSelect one of the PLL Configuration Structures.
Note
Implemented as a function call.
See also
FLL_Init, PLL_CtrlPLLSTEN, SIM_CtrlPLLVLP