MKM34Z256VLx7 Bare Metal Software Drivers  R4.1.6
Reference Manual
MPU Configuration Structures

Overview

This section describes default configuration structures for MPU module. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros

#define MPU_RGD_DI_CONFIG
 Configures region descriptor, start and end addresses, process identifier and mask to default (POR) state. Region descriptor is marked as invalid (disabled). More...
 
#define MPU_RGD_EN_GLOBAL_CONFIG
 Configures global region descriptor with start address=0x00000000, end address=0xffffffff, M0SM and M2SM=0x03 (same as M0UM and M2UM), M0UM and M2UM=0x07 (RWX access enabled) and process identifier and mask disabled. More...
 
#define MPU_RGD_EN_CM0_PID_OFF_DMA_PID_OFF_CONFIG(cm0_spvr, cm0_user, dma_spvr, dma_user, start_addr, end_addr)
 Basic configuration. Process identifier and mask are not included in the region hit evaluation on any bus master. Region descriptor is marked as valid (enabled). More...
 
#define MPU_RGD_EN_CM0_PID_ON_DMA_PID_OFF_CONFIG(cm0_spvr, cm0_user, dma_spvr, dma_user, pid, pid_mask, start_addr, end_addr)
 Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "CM0" master. Region descriptor is marked as valid (enabled). More...
 
#define MPU_RGD_EN_CM0_PID_OFF_DMA_PID_ON_CONFIG(cm0_spvr, cm0_user, dma_spvr, dma_user, pid, pid_mask, start_addr, end_addr)
 Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "DMA" master. Region descriptor is marked as valid (enabled). More...
 
#define MPU_RGD_EN_CM0_PID_ON_DMA_PID_ON_CONFIG(cm0_spvr, cm0_user, dma_spvr, dma_user, pid, pid_mask, start_addr, end_addr)
 Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "CM0" and "DMA" masters. Region descriptor is marked as valid (enabled). More...
 

Macro Definition Documentation

#define MPU_RGD_DI_CONFIG
Value:
(tMPU_RGD){ \
/* W0 */ SET(0x00000000), \
/* W1 */ SET(0x00000000), \
/* W2 */ CLR(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(0x03))| \
/* .. */ SET(MPU_WORD_M2UM(0x00))| \
/* .. */ CLR(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(0x03))| \
/* .. */ SET(MPU_WORD_M0UM(0x00)), \
/* W3 */ SET(MPU_WORD_PID(0x00))|SET(MPU_WORD_PIDMASK(0x00))| \
/* .. */ CLR(MPU_WORD_VLD_MASK), \
}

Configures region descriptor, start and end addresses, process identifier and mask to default (POR) state. Region descriptor is marked as invalid (disabled).

#define MPU_RGD_EN_GLOBAL_CONFIG
Value:
(tMPU_RGD){ \
/* W0 */ SET(0x00000000), \
/* W1 */ SET(0xffffffff), \
/* W2 */ CLR(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(0x03))| \
/* .. */ SET(MPU_WORD_M2UM(0x07))| \
/* .. */ CLR(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(0x03))| \
/* .. */ SET(MPU_WORD_M0UM(0x07)), \
/* W3 */ SET(MPU_WORD_PID(0x00))|SET(MPU_WORD_PIDMASK(0x00))| \
/* .. */ CLR(MPU_WORD_VLD_MASK), \
}

Configures global region descriptor with start address=0x00000000, end address=0xffffffff, M0SM and M2SM=0x03 (same as M0UM and M2UM), M0UM and M2UM=0x07 (RWX access enabled) and process identifier and mask disabled.

Note
Such global descriptor prevents region hit because granting permission is a higher priority than denying access for overlapping regions.
#define MPU_RGD_EN_CM0_PID_OFF_DMA_PID_OFF_CONFIG (   cm0_spvr,
  cm0_user,
  dma_spvr,
  dma_user,
  start_addr,
  end_addr 
)
Value:
(tMPU_RGD){ \
/* W0 */ SET((uint32)start_addr), \
/* W1 */ SET((uint32)end_addr), \
/* W2 */ CLR(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(dma_spvr))| \
/* .. */ SET(MPU_WORD_M2UM(dma_user))| \
/* .. */ CLR(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(cm0_spvr))| \
/* .. */ SET(MPU_WORD_M0UM(cm0_user)), \
/* W3 */ SET(MPU_WORD_PID(0x00))|SET(MPU_WORD_PIDMASK(0x00))| \
/* .. */ SET(MPU_WORD_VLD_MASK), \
}

Basic configuration. Process identifier and mask are not included in the region hit evaluation on any bus master. Region descriptor is marked as valid (enabled).

Parameters
cm0_spvrSelect one of the MPU Supervisor Mode Access Attributes.
cm0_userSelect one of the MPU User Mode Access Attributes.
dma_spvrSelect one of the MPU Supervisor Mode Access Attributes.
dma_userSelect one of the MPU User Mode Access Attributes.
start_addr32-bit 0-mod-32 byte start address of the memory region.
end_addr32-bit 31-mod-32 byte end address of the memory region.
#define MPU_RGD_EN_CM0_PID_ON_DMA_PID_OFF_CONFIG (   cm0_spvr,
  cm0_user,
  dma_spvr,
  dma_user,
  pid,
  pid_mask,
  start_addr,
  end_addr 
)
Value:
(tMPU_RGD){ \
/* W0 */ SET((uint32)start_addr), \
/* W1 */ SET((uint32)end_addr), \
/* W2 */ CLR(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(dma_spvr))| \
/* .. */ SET(MPU_WORD_M2UM(dma_user))| \
/* .. */ SET(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(cm0_spvr))| \
/* .. */ SET(MPU_WORD_M0UM(cm0_user)), \
/* W3 */ SET(MPU_WORD_PID(pid))|SET(MPU_WORD_PIDMASK(pid_mask))| \
/* .. */ SET(MPU_WORD_VLD_MASK), \
}

Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "CM0" master. Region descriptor is marked as valid (enabled).

Parameters
cm0_spvrSelect one of the MPU Supervisor Mode Access Attributes.
cm0_userSelect one of the MPU User Mode Access Attributes.
dma_spvrSelect one of the MPU Supervisor Mode Access Attributes.
dma_userSelect one of the MPU User Mode Access Attributes.
pid8-bit process identifier.
pid_mask8-bit process identifier mask.
start_addr32-bit 0-mod-32 byte start address of the memory region.
end_addr32-bit 31-mod-32 byte end address of the memory region.
#define MPU_RGD_EN_CM0_PID_OFF_DMA_PID_ON_CONFIG (   cm0_spvr,
  cm0_user,
  dma_spvr,
  dma_user,
  pid,
  pid_mask,
  start_addr,
  end_addr 
)
Value:
(tMPU_RGD){ \
/* W0 */ SET((uint32)start_addr), \
/* W1 */ SET((uint32)end_addr), \
/* W2 */ SET(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(dma_spvr))| \
/* .. */ SET(MPU_WORD_M2UM(dma_user))| \
/* .. */ CLR(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(cm0_spvr))| \
/* .. */ SET(MPU_WORD_M0UM(cm0_user)), \
/* W3 */ SET(MPU_WORD_PID(pid))|SET(MPU_WORD_PIDMASK(pid_mask))| \
/* .. */ SET(MPU_WORD_VLD_MASK), \
}

Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "DMA" master. Region descriptor is marked as valid (enabled).

Parameters
cm0_spvrSelect one of the MPU Supervisor Mode Access Attributes.
cm0_userSelect one of the MPU User Mode Access Attributes.
dma_spvrSelect one of the MPU Supervisor Mode Access Attributes.
dma_userSelect one of the MPU User Mode Access Attributes.
pid8-bit process identifier.
pid_mask8-bit process identifier mask.
start_addr32-bit 0-mod-32 byte start address of the memory region.
end_addr32-bit 31-mod-32 byte end address of the memory region.
#define MPU_RGD_EN_CM0_PID_ON_DMA_PID_ON_CONFIG (   cm0_spvr,
  cm0_user,
  dma_spvr,
  dma_user,
  pid,
  pid_mask,
  start_addr,
  end_addr 
)
Value:
(tMPU_RGD){ \
/* W0 */ SET((uint32)start_addr), \
/* W1 */ SET((uint32)end_addr), \
/* W2 */ SET(MPU_WORD_M2PE_MASK)|SET(MPU_WORD_M2SM(dma_spvr))| \
/* .. */ SET(MPU_WORD_M2UM(dma_user))| \
/* .. */ SET(MPU_WORD_M0PE_MASK)|SET(MPU_WORD_M0SM(cm0_spvr))| \
/* .. */ SET(MPU_WORD_M0UM(cm0_user)), \
/* W3 */ SET(MPU_WORD_PID(pid))|SET(MPU_WORD_PIDMASK(pid_mask))| \
/* .. */ SET(MPU_WORD_VLD_MASK), \
}

Advanced configuration. Process identifier and mask are included in the region hit evaluation of the "CM0" and "DMA" masters. Region descriptor is marked as valid (enabled).

Parameters
cm0_spvrSelect one of the MPU Supervisor Mode Access Attributes.
cm0_userSelect one of the MPU User Mode Access Attributes.
dma_spvrSelect one of the MPU Supervisor Mode Access Attributes.
dma_userSelect one of the MPU User Mode Access Attributes.
pid8-bit process identifier.
pid_mask8-bit process identifier mask.
start_addr32-bit 0-mod-32 byte start address of the memory region.
end_addr32-bit 31-mod-32 byte end address of the memory region.