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E:/PROJECTS/IOP/ADC Average/Src/ADC_Filter/ADC_Filter_Drv/src/Adc_Cfg.h File Reference

This file contains all ADC configuration structures. More...

#include "Adc.h"
#include "Derivative.h"

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Defines

#define ADC_CHANNEL_0   (uint8_t)0
#define ADC_CHANNEL_1   (uint8_t)1
#define ADC_CHANNEL_2   (uint8_t)2
#define ADC_CHANNEL_3   (uint8_t)3
#define ADC_CHANNEL_4   (uint8_t)4
#define ADC_CHANNEL_5   (uint8_t)5
#define ADC_CHANNEL_6   (uint8_t)6
#define ADC_CHANNEL_7   (uint8_t)7
#define ADC_CHANNEL_8   (uint8_t)8
#define ADC_CHANNEL_9   (uint8_t)9
#define ADC_CHANNEL_10   (uint8_t)10
#define ADC_CHANNEL_11   (uint8_t)11
#define ADC_CHANNEL_12   (uint8_t)12
#define ADC_CHANNEL_13   (uint8_t)13
#define ADC_CHANNEL_14   (uint8_t)14
#define ADC_CHANNEL_15   (uint8_t)15
#define ADC_CHANNEL_16   (uint8_t)16
#define ADC_CHANNEL_17   (uint8_t)17
#define ADC_CHANNEL_18   (uint8_t)18
#define ADC_CHANNEL_19   (uint8_t)19
#define ADC_CHANNEL_20   (uint8_t)20
#define MAX_CMDS_ALLOWED   ((uint8_t)4)
#define MAX_CONFIG_PARAMS   ((uint8_t)2)
#define MAX_ADC_CHANNELS   ((uint8_t)6)
#define ADC_ASSIGNED_CONFIG_PARAMS   ((uint8_t)0)
#define ADC_ASSIGNED_CNTRL_CMD   ((uint8_t)0)
#define ADC_CNTRL_CMD_WITH_EOQ   ((uint8_t)1)
#define ADC_CLK_4_PRESCALER   ((uint32_t)0x01)
#define ADC_CLK_8_PRESCALER   ((uint32_t)0x03)
#define ADC_CLK_16_PRESCALER   ((uint32_t)0x07)
#define ADC_EOQ_ENABLED   ((uint32_t)0x80000000)
#define ADC_CFIFO_DMA_CHANNEL   ((uint8_t)0)
#define ADC_RFIFO_DMA_CHANNEL   ((uint8_t)1)
#define ADC0_CR_REG   ((uint32_t)0x01)
#define ADC0_TSCR_REG   ((uint32_t)0x02)
#define ADC0_TBCR_REG   ((uint32_t)0x03)
#define ADC0_GCCR_REG   ((uint32_t)0x04)
#define ADC0_OCCR_REG   ((uint32_t)0x05)
#define MESSAGE_TAG_0   ((uint32_t)0x00000000)
#define MESSAGE_TAG_1   ((uint32_t)0x00100000)
#define MESSAGE_TAG_2   ((uint32_t)0x00200000)
#define MESSAGE_TAG_3   ((uint32_t)0x00300000)
#define MESSAGE_TAG_4   ((uint32_t)0x00400000)
#define MESSAGE_TAG_5   ((uint32_t)0x00500000)
#define ADC_QUEUE_PAUSE_BIT   ((uint32_t)0x40000000)
#define ADC_2_SAMPLING_CYCLES   ((uint32_t)0x00000000)
#define ADC_8_SAMPLING_CYCLES   ((uint32_t)0x00040000)
#define ADC_64_SAMPLING_CYCLES   ((uint32_t)0x00080000)
#define ADC_128_SAMPLING_CYCLES   ((uint32_t)0x000C0000)
#define ADC_FMT_UNSIGNED_RIGHT   ((uint32_t)0x00000000)
#define ADC_FMT_SIGNED_RIGHT   ((uint32_t)0x00010000)
#define ADC_SINGLE_SCAN_MODE   ((uint16_t)0x0010)
#define ADC_SEE_ENABLE_BIT   ((uint16_t)0x0400)
#define ADC_LONG_SAMPLE_TIME   ((uint32_t)(ADC_8_SAMPLING_CYCLES))
#define ADC_75_REF_CHANNEL   ((uint8_t)0x2B)
#define ADC_25_REF_CHANNEL   ((uint8_t)0x2C)
#define ADC_CAL_ENABLE   ((uint32_t)0x01000000)
#define ADC_CAL_DISABLE   ((uint32_t)0x00000000)
#define ADC_FIFO_BUFFER_0   ((uint8_t)0x00)
#define ADC_FIFO_BUFFER_1   ((uint8_t)0x01)
#define ADC_FIFO_BUFFER_2   ((uint8_t)0x02)
#define ADC_FIFO_BUFFER_3   ((uint8_t)0x03)
#define ADC_FIFO_BUFFER_4   ((uint8_t)0x04)
#define ADC_FIFO_BUFFER_5   ((uint8_t)0x05)
#define ADC_FIFO_BUFFER   ((uint8_t) ADC_FIFO_BUFFER_0)
#define ADC_IDEAL_RES75   ((uint32_t)(0x00003000))
#define ADC_IDEAL_RES25   ((uint32_t)(0x00001000))
#define ADC_CONFIGURATION_1   ((uint32_t)((uint32_t)0x80800000 | (uint32_t)(ADC_CLK_16_PRESCALER << 8) | (uint32_t)ADC0_CR_REG))
#define ADC_CONFIGURATION_2   ((uint32_t)((uint32_t)0x80800000 | (uint32_t)(ADC_CLK_4_PRESCALER << 8) | (uint32_t)ADC0_CR_REG))
#define ADC_CONFIGURATION_3   (uint32_t)0x80800701
#define ADC_CONV_CMD_1_FIFO_0   ((uint32_t)((uint32_t)ADC_QUEUE_PAUSE_BIT | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))
#define ADC_CONV_CMD_2_FIFO_0_EOQ   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))
#define ADC_CONV_CMD_3_FIFO_0   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_2_SAMPLING_CYCLES)))
#define ADC_CONV_CMD_4_FIFO_1   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_1) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))
#define ADC_CTRL_CMD_1   ((uint16_t) (ADC_SINGLE_SCAN_MODE | ADC_SEE_ENABLE_BIT))

Variables

uint32_t au32Adc_Config_Params [MAX_CONFIG_PARAMS]
uint32_t au32Adc_Conversion_Params [MAX_CMDS_ALLOWED]
uint8_t au8Adc_Port_Pins [MAX_ADC_CHANNELS]


Detailed Description

This file contains all ADC configuration structures.

Copyright (c) 2008 Freescale Semiconductor Freescale Confidential Proprietary

Author:
Freescale Semiconductor

r01160

Guadalajara Applications Laboratory RTAC Americas

Version:
0.1
Date:
6/27/2008 9:56:17 AM
History:

Define Documentation

#define ADC0_CR_REG   ((uint32_t)0x01)

ADC0 Control Register Address

#define ADC0_GCCR_REG   ((uint32_t)0x04)

ADC0 Gain Calibration Constant Register Address

#define ADC0_OCCR_REG   ((uint32_t)0x05)

ADC0 Offset Calibration Constant Register Address

#define ADC0_TBCR_REG   ((uint32_t)0x03)

ADC0 Time Base Counter Register Address

#define ADC0_TSCR_REG   ((uint32_t)0x02)

ADC0 time Stamp Register Address

#define ADC_128_SAMPLING_CYCLES   ((uint32_t)0x000C0000)

Define 128 sampling cycles for ADC measurement

#define ADC_25_REF_CHANNEL   ((uint8_t)0x2C)

#define ADC_2_SAMPLING_CYCLES   ((uint32_t)0x00000000)

Define Two sampling cycles for ADC measurement

#define ADC_64_SAMPLING_CYCLES   ((uint32_t)0x00080000)

Define 64 sampling cycles for ADC measurement

#define ADC_75_REF_CHANNEL   ((uint8_t)0x2B)

ADC Reference channels - 75% and 25%

#define ADC_8_SAMPLING_CYCLES   ((uint32_t)0x00040000)

Define Eight sampling cycles for ADC measurement

#define ADC_ASSIGNED_CNTRL_CMD   ((uint8_t)0)

points to: Message Tag = RFIFO 0, 8 Sampling Cycles, Format = unsigned right justification

#define ADC_ASSIGNED_CONFIG_PARAMS   ((uint8_t)0)

This definition helps to establish which configuration shall be used to configure
ADC0 module. The Configuration value is taken from "au32Adc_Configuration_Params"
array

#define ADC_CAL_DISABLE   ((uint32_t)0x00000000)

#define ADC_CAL_ENABLE   ((uint32_t)0x01000000)

Enables pr Disables Calibration after ADC Conversion

#define ADC_CFIFO_DMA_CHANNEL   ((uint8_t)0)

eDMA channel assigned to handle CFIFO command transfers

#define ADC_CHANNEL_0   (uint8_t)0

ADC Channel definitions used by the Filter driver to indicate which ADC channels
need to be sampled

#define ADC_CHANNEL_1   (uint8_t)1

#define ADC_CHANNEL_10   (uint8_t)10

#define ADC_CHANNEL_11   (uint8_t)11

#define ADC_CHANNEL_12   (uint8_t)12

#define ADC_CHANNEL_13   (uint8_t)13

#define ADC_CHANNEL_14   (uint8_t)14

#define ADC_CHANNEL_15   (uint8_t)15

#define ADC_CHANNEL_16   (uint8_t)16

#define ADC_CHANNEL_17   (uint8_t)17

#define ADC_CHANNEL_18   (uint8_t)18

#define ADC_CHANNEL_19   (uint8_t)19

#define ADC_CHANNEL_2   (uint8_t)2

#define ADC_CHANNEL_20   (uint8_t)20

#define ADC_CHANNEL_3   (uint8_t)3

#define ADC_CHANNEL_4   (uint8_t)4

#define ADC_CHANNEL_5   (uint8_t)5

#define ADC_CHANNEL_6   (uint8_t)6

#define ADC_CHANNEL_7   (uint8_t)7

#define ADC_CHANNEL_8   (uint8_t)8

#define ADC_CHANNEL_9   (uint8_t)9

#define ADC_CLK_16_PRESCALER   ((uint32_t)0x07)

#define ADC_CLK_4_PRESCALER   ((uint32_t)0x01)

ADC Clock Prescaler Options

#define ADC_CLK_8_PRESCALER   ((uint32_t)0x03)

#define ADC_CNTRL_CMD_WITH_EOQ   ((uint8_t)1)

points to: Message Tag = RFIFO 0, 8 Sampling Cycles, Format = unsigned right justification, EOQ enabled

#define ADC_CONFIGURATION_1   ((uint32_t)((uint32_t)0x80800000 | (uint32_t)(ADC_CLK_16_PRESCALER << 8) | (uint32_t)ADC0_CR_REG))

Configuration Command 1: ADC PS = 16 -> ADC Clock = 4 MHz, ADC0 Enabled, Write to Configuration Control Register

#define ADC_CONFIGURATION_2   ((uint32_t)((uint32_t)0x80800000 | (uint32_t)(ADC_CLK_4_PRESCALER << 8) | (uint32_t)ADC0_CR_REG))

Configuration Command 2: ADC PS = 16 -> ADC Clock = 4 MHz, ADC0 Enabled, Write to Configuration Control Register

#define ADC_CONFIGURATION_3   (uint32_t)0x80800701

#define ADC_CONV_CMD_1_FIFO_0   ((uint32_t)((uint32_t)ADC_QUEUE_PAUSE_BIT | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))

These definitions hold the Conversion Command Messages

#define ADC_CONV_CMD_2_FIFO_0_EOQ   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))

#define ADC_CONV_CMD_3_FIFO_0   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_0) | (uint32_t)(ADC_2_SAMPLING_CYCLES)))

#define ADC_CONV_CMD_4_FIFO_1   ((uint32_t)((uint32_t)ADC_EOQ_ENABLED | (uint32_t)(MESSAGE_TAG_1) | (uint32_t)(ADC_8_SAMPLING_CYCLES)))

#define ADC_CTRL_CMD_1   ((uint16_t) (ADC_SINGLE_SCAN_MODE | ADC_SEE_ENABLE_BIT))

This definition holds the parameters to indicate how a CFIFO shall work
Mode: Single Scan , Tigger: Software , SSS bit: Enabled

#define ADC_EOQ_ENABLED   ((uint32_t)0x80000000)

Enables EOQ bit in ADC Command register

#define ADC_FIFO_BUFFER   ((uint8_t) ADC_FIFO_BUFFER_0)

Holds the Adc FIFO buffer to be used by the driver

#define ADC_FIFO_BUFFER_0   ((uint8_t)0x00)

Result FIFO buffer numbers (0-5)

#define ADC_FIFO_BUFFER_1   ((uint8_t)0x01)

#define ADC_FIFO_BUFFER_2   ((uint8_t)0x02)

#define ADC_FIFO_BUFFER_3   ((uint8_t)0x03)

#define ADC_FIFO_BUFFER_4   ((uint8_t)0x04)

#define ADC_FIFO_BUFFER_5   ((uint8_t)0x05)

#define ADC_FMT_SIGNED_RIGHT   ((uint32_t)0x00010000)

#define ADC_FMT_UNSIGNED_RIGHT   ((uint32_t)0x00000000)

specifies how to format the 12-bit conversion data

#define ADC_IDEAL_RES25   ((uint32_t)(0x00001000))

#define ADC_IDEAL_RES75   ((uint32_t)(0x00003000))

Adc Reference Calibration Voltages

#define ADC_LONG_SAMPLE_TIME   ((uint32_t)(ADC_8_SAMPLING_CYCLES))

Configures Long sampling time in ADC clock cycles

#define ADC_QUEUE_PAUSE_BIT   ((uint32_t)0x40000000)

#define ADC_RFIFO_DMA_CHANNEL   ((uint8_t)1)

eDMA channel assigned to handle RFIFO data transfers

#define ADC_SEE_ENABLE_BIT   ((uint16_t)0x0400)

Enables Single-Scan bit on CFCR register

#define ADC_SINGLE_SCAN_MODE   ((uint16_t)0x0010)

Enables ADC Operating mode to single scan

#define MAX_ADC_CHANNELS   ((uint8_t)6)

This parameter indicates the amount of ADC channels that should be configured

#define MAX_CMDS_ALLOWED   ((uint8_t)4)

Maximum Commands allowed to be configured

#define MAX_CONFIG_PARAMS   ((uint8_t)2)

Maximum configuration parameters allowed to be configured

#define MESSAGE_TAG_0   ((uint32_t)0x00000000)

Indicates to ADC where the conversion result shall be stored (RFIFO 0 - 5)

#define MESSAGE_TAG_1   ((uint32_t)0x00100000)

#define MESSAGE_TAG_2   ((uint32_t)0x00200000)

#define MESSAGE_TAG_3   ((uint32_t)0x00300000)

#define MESSAGE_TAG_4   ((uint32_t)0x00400000)

#define MESSAGE_TAG_5   ((uint32_t)0x00500000)


Variable Documentation

uint32_t au32Adc_Config_Params[MAX_CONFIG_PARAMS]

ADC Configuration parameters

uint8_t au8Adc_Port_Pins[MAX_ADC_CHANNELS]

This array holds the ADC channels to be configured as inputs