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E:/PROJECTS/IOP/ADC Average/Src/ADC_Filter/ADC_Filter_Drv/src/MPC551x_HWInit.h File Reference

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Defines

#define NO_EXTERNAL_MEMORY   0
#define MPC5516DEMO_AXM_0321   1
#define INIT_USED_BOARD   NO_EXTERNAL_MEMORY
#define MAS0_VALUE(eselcam)   ((unsigned long)(0x10000000 | (eselcam << 16)))
#define MAS1_VALUE(valid, iprot, tid, ts, tsize)   ((unsigned long)((valid << 31) | (iprot << 30) | (tid << 16) | (ts << 12) | (tsize << 8)))
#define V_INVALID   0
#define V_VALID   1
#define IPROT_NOTPROTECTED   0
#define IPROT_PROTECTED   1
#define TID_GLOBAL   0
#define TSIZE_4KB   1
#define TSIZE_16KB   2
#define TSIZE_64KB   3
#define TSIZE_256KB   4
#define TSIZE_1MB   5
#define TSIZE_4MB   6
#define TSIZE_16MB   7
#define TSIZE_64MB   8
#define TSIZE_256MB   9
#define MAS2_FLAGS(sharen, w, i, m, g, e)   ((unsigned long)((sharen << 9)| (w << 4)| (i << 3)| (m << 2)| (g << 1)| (e)))
#define SHARED_CACHE_STATE_NOT_USED   0
#define SHARED_CACHE_STATE_USED   1
#define WRITE_BACK   0
#define WRITE_THROUGH   1
#define CACHEABLE   0
#define CACHE_INHIBIT   1
#define MEM_COHERENCE_NREQ   0
#define MEM_COHENRECE_REQ   1
#define NOT_GUARDED   0
#define GUARDED   1
#define BIG_ENDIAN   0
#define LITTLE_ENDIAN   1
#define MAS3_FLAGS(permissions)   ((unsigned long)(permissions))
#define READ_WRITE_EXECUTE   0x3f
#define READ_EXECUTE   0x33

Functions

__asm void INIT_Derivative (void)
__asm void INIT_ExternalBusAndMemory (void)


Define Documentation

#define BIG_ENDIAN   0

MAS2[E]: Page is accessed in big-endian order

#define CACHE_INHIBIT   1

MAS2[I]: The page is cache-inhibited

#define CACHEABLE   0

MAS2[I]: The page is considered cacheable

#define GUARDED   1

MAS2[G]: All loads and stores are performed without speculation

#define INIT_USED_BOARD   NO_EXTERNAL_MEMORY

#define IPROT_NOTPROTECTED   0

IPROT TLB Invalidate protect bit

#define IPROT_PROTECTED   1

#define LITTLE_ENDIAN   1

MAS2[E]: Page is accessed in little-endian order

#define MAS0_VALUE ( eselcam   )     ((unsigned long)(0x10000000 | (eselcam << 16)))

Generate MMU Assist 0 value from the parameters provided. In accordance with the PowerPC Zen core specification the TLBSEL value is always set to 01b to maintain future compatibility.

#define MAS1_VALUE ( valid,
iprot,
tid,
ts,
tsize   )     ((unsigned long)((valid << 31) | (iprot << 30) | (tid << 16) | (ts << 12) | (tsize << 8)))

Generate MMU Assist 1 value from the parameters provided

parameter valid: 1 if the MMU entry is valid, otherwise 0 (invalid). parameter iprot: Invalidation protection value parameter tid: the translation ID parameter ts: the translation space value parameter tsize: the translation size

#define MAS2_FLAGS ( sharen,
w,
i,
m,
g,
 )     ((unsigned long)((sharen << 9)| (w << 4)| (i << 3)| (m << 2)| (g << 1)| (e)))

Generate MMU Assist 2 value from the parameters provided

Effective Page Number (start address of logical memory region) must be computed directely in the assembly code.

parameter w: Write-through Required parameter i: Cache Inhibited parameter m: Memory Coherency Required parameter g: Guarded parameter e: Endianness

#define MAS3_FLAGS ( permissions   )     ((unsigned long)(permissions))

Generate MMU Assist 3 flags from the parameters provided

Real Page Number (start address of physical memory region) must be computed directely in the assembly code

parameter permissions: Permission bits

#define MEM_COHENRECE_REQ   1

MAS2[M]: Memory Coherence is required

#define MEM_COHERENCE_NREQ   0

MAS2[M]: Memory Coherence is not-required

#define MPC5516DEMO_AXM_0321   1

#define NO_EXTERNAL_MEMORY   0

#define NOT_GUARDED   0

MAS2[G]: Access to page is not guarded

#define READ_EXECUTE   0x33

MAS3[U/S{XWR}]: Read and Execute permission

#define READ_WRITE_EXECUTE   0x3f

MAS3[U/S{XWR}]: Read. Write and Execute permission

#define SHARED_CACHE_STATE_NOT_USED   0

MAS2[SHAREN]: Cache fills do not use the shared cache state for this page.

#define SHARED_CACHE_STATE_USED   1

MAS2[SHAREN]: Cache fills use the shared cache state for this page.

#define TID_GLOBAL   0

Translation ID defines the TID as global and matches all process IDs

#define TSIZE_16KB   2

#define TSIZE_16MB   7

#define TSIZE_1MB   5

#define TSIZE_256KB   4

#define TSIZE_256MB   9

#define TSIZE_4KB   1

Translation size

#define TSIZE_4MB   6

#define TSIZE_64KB   3

#define TSIZE_64MB   8

#define V_INVALID   0

V TLB valid bit

#define V_VALID   1

#define WRITE_BACK   0

MAS2[W]: Update data in the cache only

#define WRITE_THROUGH   1

MAS2[W]: All stores performed are written through to memory


Function Documentation

__asm void INIT_Derivative ( void   ) 

__asm void INIT_ExternalBusAndMemory ( void   )