NFMI Radio for Wireless Audio and Data Streaming

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Product Details

Features

Controller subsystem

  • Customer programmable Arm Cortex-M0 ultra-low-power, for system configuration and control
  • I²C-bus/SPI follower control interface
  • Flexible interfaces: UART, GPIO, SWD, SPI leader, I²C-bus controller
  • Embedded low power 512 kbit EEPROM

Magnetic induction transceiver

  • 596 kbit/s raw throughput
  • Carrier frequency of 10.579 MHz
  • On-chip tuning of coil resonator tank
  • Programmable transmit power
  • Integrated AGC
  • Operation from internal oscillator
  • Optimized protocol for low latency ear-to-ear communication
  • Embedded network protocol for up to 15 devices

Audio data path

  • I2S-bus audio interface
  • Support for multiple audio sample frequencies up to 48 kHz
  • Integrated MAC accelerator for MI radio
  • Integrated audio G.722 and ADPCM codecs for up to four audio channels
  • Integrated latency controller for two RX channels
  • Integrated adaptive sample rate converter for two RX channels
  • Integrated CoolFlux DSP with SBC codec

Power management subsystem

  • Integrated battery management supporting ZnAir or NiMH batteries
  • Integrated supply booster for transparent EEPROM operation

Power consumption

  • Supports multiple low-power modes:
    • Power-down: 5 μA
    • Deep-sleep: 8 μA
    • Sleep: 60 μA
    • Carrier detect: 100 μA
    • Mono audio streaming - receive: 1000 μA (fs = 20 kHz, G.722)
    • Mono audio streaming - transmit: 1050 μA (fs = 20 kHz, G.722)
    • Binaural audio streaming: 1300 μA (fs = 20 kHz, G.722)
    • Mono audio streaming - receive: 2400 μA (fs = 44.1 kHz, SBC)
    • Mono audio streaming - transmit: 2000 μA (fs = 44.1 kHz, SBC)
  • Support for flexible slot allocation of the radio enabling better power tuning over the different use cases
  • Integrated ultra-low-power oscillator and timer used in low-power modes

Package

  • WLCSP31 with dimensions of 2.79 mm × 3.72 mm (10.38 mm2)
  • Flexible I/O switch matrix with 14 pins
  • Configurable supply level for I/O
  • 31 bumps with a minimum pitch of 400 μm

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Documentation

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3 documents

Design Files

Software

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