LPC4370FET100|Arm Cortex-M4/M0|32-bit MCU

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The LPC4370 are Arm Cortex-M4 based microcontrollers for embedded applications which include an Arm Cortex-M0 coprocessor and an Arm Cortex-M0 subsystem for managing peripherals, 282 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC4370 operate at CPU frequencies of up to 204 MHz.

The Arm Cortex-M4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core.

The LPC4370 include an application Arm Cortex-M0 coprocessor and a second Arm Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The Arm Cortex-M0 core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with a simple instruction set and reduced code size.

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Data Sheet

Application Notes

Product Details

Features

Main Cortex-M4 processor:
- Arm Cortex-M4 processor, running at frequencies of up to 204 MHz
- Arm Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions
- Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
- Hardware floating-point unit
- Non-maskable Interrupt (NMI) input
- JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
- System tick timer
Cortex-M0 coprocessor:
- Arm Cortex-M0 coprocessor capable of off-loading the main Arm Cortex-M4 processor
- Running at frequencies of up to 204 MHz
- JTAG and built-in NVIC
Cortex-M0 subsystem:
- Arm Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on a separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM
- Running at frequencies of up to 204 MHz
- Connected via a core-to-core bridge to the main AHB multilayer matrix and the main Arm Cortex-M4 processor
- JTAG and built-in NVIC
On-chip memory:
- 264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kB of SRAM on the Cortex-M0 subsystem
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually
- 64 kB ROM containing boot code and on-chip software drivers
- 64-bit + 256 bit general-purpose One-Time Programmable (OTP) memory
Configurable digital peripherals:
- Serial GPIO (SGPIO) interface
- State Configurable Timer (SCT) subsystem on AHB
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1
Serial interfaces:
- Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2)
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY
- USB interface electrical test software included in ROM USB stack
- One 550 UART with DMA support and full modem interface
- Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface
- Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support
- One SPI controller
- One Fast-mode Plus I²C-bus interface with monitor mode and open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to 1 Mbit/s
- One standard I²C-bus interface with monitor mode and with standard I/O pins
- Two I²S interfaces, each with DMA support and with one input and one output
Digital peripherals:
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices
- LCD controller with DMA support and a programmable display resolution of up to 1024 H x 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping
- Secure Digital Input Output (SD/MMC) card interface
- Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB followers
- 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain mode
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins
- Four general-purpose timer/counters with capture and match capabilities
- One motor control Pulse Width Modulator (PWM) for three-phase motor control
- One Quadrature Encoder Interface (QEI)
- Repetitive Interrupt timer (RI timer)
- Windowed watchdog timer (WWDT)
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers
- Alarm timer; can be battery powered
Analog peripherals:
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. LBGA256 package only
- Two 8-channel, 10-bit ADCs (ADC0/1) with DMA support and a data conversion rate of 400 kSamples/s for a total of 16 independent channels. The 10-bit ADCs are only available on the LBGA256 package
- One 6-channel, 12-bit high-speed ADC (ADCHS) with DMA support and a data conversion rate of 80 MSamples/s
Unique ID for each device
Clock generation unit:
- Crystal oscillator with an operating range of 1 MHz to 25 MHz
- 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and voltage
- Ultra-low power Real-Time Clock (RTC) crystal oscillator
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL
- Clock output
Power:
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain
- RTC power domain can be powered separately by a 3 V battery supply
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain
- Brownout detect with four separate thresholds for interrupt and forced reset
Available as LBGA256 and TFBGA100 packages

Target Applications

Motor control
Power management
White goods
RFID readers
Embedded audio applications
Industrial automation
e-metering

Part numbers include: LPC4370FET100.

Buy/Parametrics

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Documentation

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1-5 of 18 documents

^{Data Sheet}
32-bit Arm^® Cortex^®-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet; two HS USBs; 80 Msps 12-bit ADC; configurable peripherals

PDFRev 2.4Mar 15, 20167.1 MBLPC4370English
^{Application Note}
USBD Library for LPC4300/LPC1800 series MCUs

ZIPRev 1.0Jul 9, 20188.6 MBTN00041English
^{Application Note}
Connecting TFT LCD with LCD controller of LPC MCU

ZIPRev 1Aug 22, 20173.2 MBAN12027English
^{Application Note}
SCTimer/PWM cookbook

ZIPRev 5.0Mar 22, 201625.5 MBAN11538English, 中文
^{Application Note}
Code Read Protection in LPC1800 and LPC4300

ZIPRev 1.0Aug 14, 201416.6 MBAN11581English
^{Application Note}
Implementing PWM dithering on the LPC18xx SCTimer/PWM

ZIPRev 1.0Aug 8, 20141.7 MBAN11580English
^{Application Note}
SCT camera interface design with LPC1800 and LPC4300

ZIPRev 1.2Jun 12, 20141.4 MBAN11365English
^{Application Note}
AES encryption and decryption software on LPC microcontrollers

ZIPRev 1.1Mar 17, 2014177.9 KBAN11241English
^{Application Note}
SDRAM interface to LPC18xx/43xx EMC

PDFRev 1.0Jan 31, 2014351.0 KBAN11508English
^{Application Note}
Implementing a UART using SGPIO on LPC4300

ZIPRev 1.0Jul 22, 20131.7 MBAN11351English
^{Application Note}
SGPIO camera module design using LPC4300

ZIPRev 1.0Jul 22, 20134.1 MBAN11343English
^{Application Note}
How to implement the PMBus software stack

ZIPRev 1.0Jul 22, 20131.1 MBAN11318English
^{User Guide}
LPC43xx/LPC43Sxx Arm® Cortex®-M4/M0 multi-core microcontroller

PDFRev 2.5Sep 13, 201913.6 MBUM10503English
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^Brochure
Cortex-M4 MCUs with Cortex-M0 coprocessor, HS USB, and more

PDFRev 1.0Oct 30, 20131.0 MB75017486English
^Errata
Errata sheet LPC4370, LPC4350, LPC4330, LPC4320, LPC4310

PDFRev 7.2Feb 10, 20231.4 MBES_LPC43X0English
^{Package Information}
plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm

PDFRev 1.0Feb 8, 2016424.0 KBSOT926-1English
^{Training Presentation}
Driving LPC1700/LPC1800/LPC4300 with EPSON Crystals

PDFRev 1.1Nov 27, 2015213.7 KBR_10076English
^{Supporting Information}
Connecting a USB power switch to the LPC18xx / LPC43xx

PDFRev 1.0Mar 6, 201376.0 KBTN00007English

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Design Resources

Design Files

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4 design files

Receive the full breakdown. See the product footprint and more in the eCad file.

^Models
IBIS models for LPC18x0 and LPC43x0 FBD208

ZIPRev 2Mar 25, 2020 16:19:00377.1 KBIBIS_LPC18x0_LPC43x0FBD208
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BSDL for LPC18xx and LPC43xx

ZIPRev 2Feb 27, 2018 11:57:00269.0 KBBSDL_LPC18XX_43XX
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^Models
IBIS models for LPC18x0 and LPC43x0 FET256-180-100

ZIPRev 1Jun 13, 2017 16:19:00380.3 KBIBIS_LPC18x0_43x0FET256-180-100
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^{Symbols and Footprints}
LPC18XX_43XX_SCH Orcad Symbols

ZIPRev 1.0Apr 30, 2018 12:37:0052.2 KBLPC18XX_43XX_SCH_1
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