16-Bit I²C-Bus and SMBus Low-Power I/O Port with Interrupt and Reset | NXP Semiconductors

16-Bit I²C-Bus and SMBus Low-Power I/O Port with Interrupt and Reset

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Product Details

Block Diagram

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PCA9539_PCA9539R

PCA9539_PCA9539R Block Diagram

PCA9539BS, PCA9539D, PCA9539PW, PCA9539RBS, PCA9539RPW

Features

Key Features

  • 16-bit I²C-bus GPIO with interrupt and reset
  • Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9539PW/Q900 and PCA9539RPW/Q900)
  • 5 V tolerant I/Os
  • Polarity inversion register
  • Active LOW interrupt output
  • Active LOW reset input
  • Low standby current
  • Noise filter on SCL/SDA inputs
  • No glitch on power-up
  • Internal power-on reset
  • 16 I/O pins which default to 16 inputs
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Offered in three different packages: SO24, TSSOP24 and HVQFN24

Buy/Parametrics

2 results

Include 3 NRND

Order

CAD Model

No of bits

VDD [min]

VDD [max]

Over volt tolerant

No of supplies

Standby current [typ] (µA)

Max Sink Current per bit (mA)

Max Sink Current, per package (mA)

Source Current per bit (mA)

Interrupt output pin

Reset input pin

Output mode

Input mode: invert option

I2C-bus (kHz)

Footprint body and leads

Package Type

Operating Temperature (°C)

No of Addresses

Remark

16

2.3

5.5

Y

1

0.25

25

200

10

Y

Y

Totem pole

Y

400

52.14

TSSOP24

-40~85

4

16

2.3

5.5

Y

1

0.25

25

200

10

Y

Y

Totem pole

Y

400

52.14

TSSOP24

-40~85

4

Only I2C state machine is reset with hardware pin

Documentation

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1-10 of 16 documents

Compact List

Application Note (3)
Brochure (2)
Data Sheet (1)
Package Information (3)
Packing Information (5)
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Design Files

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1-5of 7 design files

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Hardware

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1 hardware offering

Engineering Services

1 engineering service

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