Design Files
Quick reference to our
design files types.
1 design file
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Models
P82B96 IBIS model
Dual Bidirectional Bus Buffer
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface between the normal IC-bus and a range of other bus configurations. It can interface IC-bus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350 A SMBus, to 3.3 V logic devices, and to 15 V levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal IC-bus protocols or clock speed. The IC adds minimal loading to the IC-bus node, and loadings of the new bus or remote IC-bus nodes are not transmitted or transformed to the local node. Restrictions on the number of IC-bus devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bidirectional signal line with IC-bus properties.
S08 Package
Product Details
Features
General
- Bidirectional data transfer of IC-bus signals
- Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
- Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive buses
- 400 kHz operation over at least 20 meters of wire (see AN10148)
- Supply voltage range of 2 V to 15 V with IC-bus logic levels on Sx/Sy side independent of supply voltage
- Splits IC-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths.
- Low power supply current
- ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101
- Latch-up free (bipolar process with no latching structures)
- Packages offered: DIP8, SO8 and TSSOP8
- Interface between I²C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V)
- Interface between I²C-bus and SMBus (350 µA) standard
- Simple conversion of I²C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250
- Interfaces with opto-couplers to provide opto-isolation between I²C-bus nodes up to 400 kHz
- Ambient operating temperature -40 °C (Min), 85 °C (Max)
- Supply voltage 2 V (Min), 15 V (Max)
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Documentation
Quick reference to our documentation types.
1-5 of 20 documents
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Data Sheet
Dual bidirectional bus buffer
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Application Note
Sending I2C-bus signals via long communications cables
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Application Note
Very large I2C-bus systems and long buses
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Application Note
Features and applications of the P82B715 I2C-bus extender
Design Resources
Engineering Services
To get further assistance directly from NXP, please see our Engineering Services.
1 engineering service
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Independent Design House (IDH)
Embedded Software Design
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