High-Performance DisplayPort Gen2 2-1 Multiplexer | NXP Semiconductors

High-Performance DisplayPort Gen2 2-1 Multiplexer

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Block Diagram

CBTL06DP212 Block Diagram

CBTL06DP212 Block Diagram

Features

Key Features

  • High-bandwidth: 5 GHz at -3 dB
  • Low crosstalk: -35 dB at 3 GHz
  • Low off-state isolation: -30 dB at 3 GHz
  • Low return loss: -8 dB at 3 GHz
  • Very low intra-pair skew (5 ps typical)
  • Very low inter-pair skew (< 80 ps)
  • Switch/multiplexer position select CMOS input
  • DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
  • Supports HDMI/DVI incorrect dongle connection
  • Single 3.3 V power supply
  • Operation current of 2 mA typical
  • ESD 8 kV HBM, 1 kV CDM
  • ESD 2 kV HBM, 500 V CDM for control pins
  • Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package

1 : 2 Switching or 2 : 1 Multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) Signals

  • 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort main link signals
  • 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
  • 1 channel with 2 : 1 multiplexing/switching for HPD signal

Low Insertion Loss

  • -0.5 dB at 100 MHz
  • -3 dB at 5 GHz

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Documentation

Quick reference to our documentation types.

3 documents

Compact List

Design Files

Engineering Services

2 engineering services

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