The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs.
1 result
Include 0 NRND
Part | Order | CAD Model | Status | Signal Application | Type VLT | Number of bits | VCC(A) (Min - Max) | VCC(B) (Min-Max) | Supply Current (Typ) (μA) | Supply Current (Max) (μA) | Input Type (TTL, CMOS, Schmitt Trigger) | Output Type (Open Drain, 3-State, Push-Pull, Pass-gate) | Ambient Operating Temperature (Min to Max) (℃) | AEC-Q100 compliant | Package Type | Package Dimensions (LxWxZ (mm)) | Budgetary Price excluding tax |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Active | GTL bus | LVTTL to GTL w/ Direction Pin | 8 | 0 to 3.6 | 0 to 5.5 | 8000 | 12000 | LVTTL | GTL (Open-drain) | -40 to 85 | N | TSSOP24 | 7.8 x 4.4 x 1.1 | 1K @ US$0.84 |
Quick reference to our documentation types.
6 documents
Compact List
6 documents
Compact List
1 design file
To get further assistance directly from NXP, please see our Engineering Services.
2 engineering services
To find additional partner offerings that support this product, visit our Partner Marketplace.
There are no recently viewed products to display.
