4-Bit GTL-to-GTL Buffer | NXP Semiconductors

4-Bit GTL-to-GTL Buffer

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Product Details

Block Diagram

Choose a diagram:

GTL2034 Block Diagram

GTL2034 Block Diagram

Block diagram: GTL2034PW

Features

  • Operates as a 4-bit GTL-/GTL/GTL+ to GTL-/GTL/GTL+ bus buffer
  • 3.0 V to 3.6 V operation
  • GTL input and output 3.6 V tolerant
  • Vref adjustable from 0.5 V to VCC /2
  • Partial power-down permitted
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101
  • Latch-up protection exceeds 500 mA per JESD78
  • Package offered: TSSOP14

Buy/Parametrics

1 result

Include 0 NRND

Order

CAD Model

Status

Signal Application

Type VLT

Number of bits

VCC(A) (Min - Max)

VCC(B) (Min-Max)

Supply Current (Typ) (μA)

Supply Current (Max) (μA)

Input Type (TTL, CMOS, Schmitt Trigger)

Output Type (Open Drain, 3-State, Push-Pull, Pass-gate)

Ambient Operating Temperature (Min to Max) (℃)

AEC-Q100 compliant

Package Type

Package Dimensions (LxWxZ (mm))

Budgetary Price excluding tax

Active

GTL bus

GTL to GTL

4

0 to 3.6

0 to 3.6

4000

8000

GTL

GTL (Open-drain)

-40 to 85

N

TSSOP14

5 x 4.4 x 1.1

1K @ US$0.66

Documentation

Quick reference to our documentation types.

6 documents

Compact List

Application Note (1)
  • AN10216[AN10216]
Data Sheet (1)
Package Information (1)
Packing Information (1)
Selector Guide (1)
Training Presentation (1)

Design Files

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2 design files

Engineering Services

2 engineering services

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