2-Bit LVTTL-to-GTL Transceiver | NXP Semiconductors

2-Bit LVTTL-to-GTL Transceiver

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Product Details

Block Diagram

GTL2012 Block Diagram

GTL2012 Block Diagram

Features

  • Operates as a 2-bit GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
  • GTL input and output 3.6 V tolerant
  • Vref adjustable from 0.5 V to 0.5VCC
  • Partial power-down permitted
  • Latch-up protection exceeds 500 mA per JESD78
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101
  • Package offered: TSSOP8 (MSOP8) and VSSOP8

Buy/Parametrics

1 result

Include 0 NRND

Order

CAD Model

Status

Signal Application

Type VLT

Number of bits

VCC(A) (Min - Max)

VCC(B) (Min-Max)

Supply Current (Typ) (μA)

Supply Current (Max) (μA)

Input Type (TTL, CMOS, Schmitt Trigger)

Output Type (Open Drain, 3-State, Push-Pull, Pass-gate)

Package Type

Package Dimensions (LxWxZ (mm))

Ambient Operating Temperature (Min to Max) (℃)

AEC-Q100 compliant

Budgetary Price excluding tax

Active

GTL bus

LVTTL to GTL w/ Direction Pin

2

0 to 3.6

0 to 5.5

4000

10000

LVTTL

GTL (Open-drain)

TSSOP8

3 x 3 x 1.1

-40 to 85

N

1K @ US$0.42

Documentation

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1-5 of 6 documents

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Design Files

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2 design files

Engineering Services

2 engineering services

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