GTL2008PW | NXP Semiconductors

12-Bit GTL-to-LVTTL Translator with Power Good Control and High-Impedance LVTTL and GTL Outputs

  • This page contains information on a product that is no longer manufactured (discontinued). Specifications and information herein are available for historical reference only.

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Product Details

Block Diagram

Block diagram: GTL2008PW

Features

Key Features

  • Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
  • Operates at GTL-/GTL/GTL+ signal levels
  • EN1 and EN2 disable error output
  • All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are LOW
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 O
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA
  • Package offered: TSSOP28

Buy/Parametrics

1 result

Exclude 1 NRND

CAD Model

Application

Function

Operating Temperature (°C)

Voltage Translation Range

TTL Drive

GTL Drive

Number of bits

Dual Xeon Processor Interface to 3.3V Chipset with power good enable

12-bit GTL-/GTL/GTL+ to LVTTL translator

-40~85

0.5 to 3.6 ~ 3.0 to 5.5

16

15

12

Documentation

Quick reference to our documentation types.

5 documents

Compact List

Application Note (1)
  • AN10216[AN10216]
Data Sheet (1)
Package Information (1)
Packing Information (1)
Training Presentation (1)

Design Files

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2 design files

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