MPC5566|32-bit MCU|Powertrain

For best experience this site requires Javascript to be enabled. To enable on your browser, follow our accessibility instructions.

Designed for engine management, the NXP^® MPC5566 embedded controller provides developers with a cost-effective medium to support more sophisticated, memory-intensive timing and control functionality.

Helps increase fuel efficiency and improved emissions
Allows more advanced engine control systems to be deployed
Enables easy migration to next-generation 3 MB flash-embedded controllers
Offers system performance of up to five times that of its MPC500 predecessors
Ideal for any application that requires complex, real-time control
Qualifies for the harshest automotive environments
Pin-and code-compatible with other MPC5500 family MCUs

Data Sheet

Reference Manual

Product Details

Block Diagram

MPC5566 Block Diagram

Get diagram PDF

Features

Our e200z6 Core

High-performance 132 MHz 32-bit Power Architecture technology core with variable length encoding (VLE)
Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

3 MB of embedded flash memory with error correction coding (ECC) and RWW
128 KB on-chip static RAM with ECC
32 KB of cache (with line-locking) that can be configured as additional RAM

System

Two enhanced time processor units (eTPUs), each with 32 I/O channels and 24 KB of designated SRAM
64-channel eDMA (enhanced direct memory access) controller
Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
MPC500 compatible external bus interface
Nexus IEEE^{^®}-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
416-pin PBGA package
Temperature range: -40 to 125ºC

I/O

40-channel dual enhanced queued analog-to-digital converters (eQADC)—each up to 12 bit resolution and up to 1.25 us conversions, six queues with triggering and DMA support
Four deserial serial peripheral interface (DSPI) modules—16 bits wide up to six chip selects each
Four controller area network (CAN) modules with 64 buffers each
Two enhanced serial communication interface (eSCI) modules
24-channel enhanced multiple I/O system (EMIOS) with unified channels

Included in NXP ®.s product longevity program

Product longevity program with assured supply for a minimum of 15 years after launch

Buy/Parametrics

‌ ‌ ‌	‌ ‌	‌ ‌	‌ ‌	‌ ‌	‌ ‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌
‌ ‌ ‌	‌	‌	‌	‌	‌