S32R26 and S32R27 Microcontrollers for High-Performance Radar

  • Instead, use the S32R294 MCUs, designed to extend the existing S32R product family that already includes the MPC5775K, S32R274 and the S32R372 devices. If you are still interested in S32R37 MCUs, please contact NXP support.

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Block Diagram

S32R2x Block Diagram

S32R2x Block Diagram

Features

Key Features

  • Dual Power Architecture® e200z7 32-bit CPU
  • Dual Power Architecture e200z4 32-bit CPU with checker core (available in lock-step operation)
  • 2 MB flash with ECC
  • 1.5 MB SRAM with ECC
  • Radar Signal Processing Toolbox (SPT 2.0)
  • Radar interfaces: MIPI-CSI2 (4 data lanes)
  • Safety: ISO 26262 SEooC up to ASIL D
  • Security: CSE2 (Cryptographic Services Engine)
  • -40 to 150˚ C (junction) temperature
  • Interfaces: Zipwire, 2x SAR-ADC, 2x SPI, 2x I2C, 3x FlexCAN (including 2x CAN FD), Flexray, LINFlexD, Ethernet
  • AFEPLL
  • Improved EMC performance in the GLONASS band (when using S32R264)
  • SDPLL
  • Radar interfaces: ΣΔ-ADC (4x 12-bit,10 MSps) and DAC (10 MSps)

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Documentation

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Design Files

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Hardware

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Software

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

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