LPC552x/S2x

LPC552x/S2x | Arm®Cortex®-M33 | 32-bit MCUs | NXP Semiconductors

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The LPC552x/S2x MCU family is part of the EdgeVerse™ edge computing platform and further expands the world’s first general purpose Cortex-M33-based MCU series, offering significant advantages for developers, including pin-, software- and peripheral-compatibility for ease of use and accelerating time to market, while leveraging the cost-effective 40-nm NVM process technology.

The LPC552x/S2x is a mainstream family within the LPC5500 MCU series inclusive of LPC55S28, LPC55S26, LPC5528, LPC5526 MCUs, providing a perfect balance between security, performance efficiency and system integration for general embedded and industrial IoT markets. The LPC552x/S2x MCU family combines the high-performance efficiency of the Cortex-M33 core with multiple high-speed interfaces, an integrated power management IC, and rich analog integration.

Data Sheet

Application Notes

Product Details

Block Diagram

LPC552x/S2x MCU

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Features

Arm Cortex-M33 Core

Running at a frequency of up to 150 MHz
Floating Point Unit (FPU) and Memory Protection Unit (MPU)
Arm Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC)
Non-maskable Interrupt (NMI) input with a selection of sources
Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities
System tick timer

On-Chip Memory

Up to 512 kB on-chip flash program memory with flash accelerator and 512 byte page erase and write
Up to 512 kB total SRAM consisting of 32 kB SRAM on Code Bus, 192 kB SRAM on System Bus (192 kB is contiguous), 16 kB SRAM on System bus, and additional 16 kB USB SRAM on System Bus, which can be used by the USB interface or for general purpose use

Security Features

PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection*
CASPER Crypto coprocessor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC)*
AES-256 encryption/decryption engine*
Secure Hash Algorithm (SHA2) module supporting secure boot with dedicated DMA controller*
Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction*
128-bit unique device serial number for identification (UUID)
Secure GPIO*
Random Number Generator (RNG)
Secure Boot support*

* = Secured Products only (LPC55S2x)

Serial Interfaces

FlexComm Interface contains up to nine serial peripherals. Each FlexComm Interface can be selected by software to be a USART, SPI, I²C, and I²S interface
I²C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1 Mbit/s and with multiple address recognition and monitor mode
USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode
USB 2.0 high-speed host/device controller with on-chip high-speed PHY

Digital Peripherals

DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals
DMA1 controller with 10 channels and up to 16 programmable triggers, able to access all memories and DMA-capable peripherals
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO with support for up to two cards. Supported card types are MMC, SDIO, and CE-ATA. Supports SD2.0, and SR25
CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support
Up to 64 General-Purpose Input/Output (GPIO) pins
GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports
Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising, falling or both input edges
Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states
I/O pin configuration with support for up to 16 function options
Programmable Logic Unit (PLU) to create small combinational and/or sequential logic networks including state machines

Analog Peripherals

16-bit ADC with five differential channel pair (or 10 singled-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 1.0MSamples/sec. The ADC supports two independent conversion sequences
Integrated temperature sensor connected to the ADC
Comparator with five input pins and external or internal reference voltage
Timers
Five 32-bit standard general purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs. Specific timer events can be selected to generate DMA requests
One SCTimer/PWM with eight input and ten output functions (including capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 32 states
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
Windowed Watchdog Timer (WWDT) with FRO 1 MHZ as a clock source
Micro-Tick Timer running from the watchdog oscillator can be sued to wake-up the device from sleep and deep-sleep modes
42-bit free running OS Timer as continuous timebase for the system, available in any reduced power modes

Clock Generation

Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to +/- 1% accuracy over the entire voltage and temperature range
32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 1% accuracy over the entire voltage and temperature range
Internal low power oscillator (FRO 1 MHz)
Crystal oscillator with an operating frequency of 1 MHz to 25 MHz. Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz
Crystal oscillator with 32.768 kHz operating frequency
PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the need for a high-frequency external clock
Clock output function with divider to monitor internal clocks
Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal

Power-Saving Modes

Integrated Power Management Unit (PMU) to minimize power consumption
Reduced power modes: Sleep, deep-sleep with RAM retention, power-down with RAM retention and CPU0 retention, and deep power-down
Configurable wake-up options from peripheral interrupts
The Micro-Tick Timer running from the watchdog oscillator, and the Real-Time Clock (RTC) running from the 32.678 kHz clock, can be used to wake-up the device from sleep and deep-sleep modes
Power-On Reset (POR)
Brown-Out-Detect (BOD) with separate thresholds for interrupt and forced reset

Additional Information

Operating from an internal DC-DC converter
Single power supply 1.8 V to 3.6 V
JTAG boundary scan supported
Operating temperature range -40 °C to +105 °C
Available in HLQFP100 and VFBGA98 packages

Part Show description	Status	Budgetary Price ($US)	Package Type
LPC5526JBD100 Data Sheet	Active	10K @ US$2.66	HLQFP100
LPC5526JBD64 Data Sheet	Active	10K @ US$2.36	HTQFP64
LPC5526JEV98 Data Sheet	Active	10K @ US$2.59	VFBGA98
LPC5528JBD100 Data Sheet	Active	10K @ US$3.01	HLQFP100
LPC5528JBD64 Data Sheet	Active	10K @ US$2.66	HTQFP64
LPC5528JEV98 Data Sheet	Active	10K @ US$2.94	VFBGA98
LPC55S26JBD100 Data Sheet	Active	10K @ US$2.86	HLQFP100
LPC55S26JBD64 Data Sheet	Active	10K @ US$2.52	HTQFP64
LPC55S26JEV98 Data Sheet	Active	10K @ US$2.79	VFBGA98
LPC55S28JBD100 Data Sheet	Active	10K @ US$3.19	HLQFP100

Design Resources

Design Files

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Models
IBIS files for the LPC552x

ZIPRev 1.1Jun 3, 20216.3 MBLPC552X-IBIS
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IBIS files for the LPC55S2x

ZIPRev 1.1Jun 3, 20216.3 MBLPC55S2X-IBIS
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BSDL files for the LPC55S2x

ZIPRev 1.1Jul 1, 202113.2 KBLPC55S2X-BSDL
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BSDL files for the LPC552x

ZIPRev 1.1Jul 1, 202113.1 KBLPC552X-BSDL
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