LPC550x/S0x|Arm®Cortex®-M33|32-bit Microcontrollers (MCUs)

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The baseline LPC550x/S0x MCU family, with it’s lower cost options and smaller footprint, further expand the existing general-purpose LPC5500 MCU series. It's advanced security and safety integration offer applications an extra level of protection.

Offering excellent ecosystem advantages for developers, including pin-, software- and peripheral-compatibility in addition to a comprehensive portfolio of software and tools, the LPC550x/S0x MCU family helps accelerate time to market.

This family of MCUs is part of the EdgeVerse™ edge computing platform and inclusive of the LPC55S06, LPC55S04, LPC5506 and LPC5504 MCUs.

Data Sheet

Application Notes

Product Details

Block Diagram

LPC550x MCU

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Features

Arm Cortex-M33 Core

Running at frequency of up to 96 MHz
Arm TrustZone^®, floating point unit (FPU) and memory protection unit (MPU)
Cortex-M33 built-in nested vectored interrupt controller (NVIC)
Non-maskable interrupt (NMI) input with a selection of sources
Serial wire debug with eight breakpoints and four watch points. Includes serial wire output for enhanced debug capabilities
System tick timer

On-Chip Memory

Up to 256 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write
Up to 96 KB total SRAM consisting of 16 KB SRAM on code bus, 64 KB SRAM on system bus (64 KB is contiguous), and additional 16 KB SRAM on system bus

Security Features

Arm TrustZone^® enabled
PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection*
CASPER crypto coprocessor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as elliptic curve cryptography (ECC)
AES-256 encryption/decryption engine*
Secure hash algorithm (SHA2) module supporting secure boot with dedicated DMA controller*
Physical unclonable function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 bits to 4096 bits. Includes hardware for key extraction*
128-bit unique device serial number for identification (UUID)*
Secure GPIO*
True random number generator (TRNG)
Code watchdog

Serial Interfaces

The FlexComm interface contains up to nine serial peripherals. Each FlexComm interface can be selected by software to be a USART, SPI, I²C and I²S interface
I²C-bus interfaces support Fast-mode and fast-mode plus with data rates of up to 1 Mbit/s and with multiple address recognition and monitor mode

Digital Peripherals

DMA0 controller with 22 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals
DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals
CAN FD module with dedicated DMA controller
CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support
Up to 45 general-purpose input/output (GPIO) pins
GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports
Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states
I/O pin configuration with support for up to 16 function options
Programmable logic unit (PLU) to create small combinational and/or sequential logic networks including state machines

Analog Peripherals

16-bit ADC with five differential channel pair (or 10 single-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 2.0 M samples/sec. In single-ended mode, the ADC supports 2 simultaneous conversions, on input channels belonging to a differential pair
Integrated temperature sensor connected to the ADC
Comparator with five input pins and external or internal reference voltage

Timers

Five 32-bit standard general purpose asynchronous timers/counters that support up to four capture inputs and four compare outputs. Specific timer events can be selected to generate DMA requests
One SCTimer/PWM with eight input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to/from external pins and internally to/from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events and 32 states
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. Another timer in the RTC can be used for wake-up from all low-power modes including deep power down, with 1 ms resolution
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
Windowed watchdog timer (WWDT) with FRO 1 MHZ as a clock source
Micro-tick timer running from the watchdog oscillator can be used to wake the device up from sleep and deep-sleep modes
42-bit free running OS Timer as a continuous timebase for the system, available in any reduced power modes

Clock Generation

96 MHz/12 MHz internal free running oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a divided down 12 MHz output that can be used as a system clock. The FRO is trimmed to +/- 1% accuracy over the entire voltage (from 0 C to 85 C). The FRO is trimmed to +/- 2% accuracy over the entire voltage and -40 °C to 105 °C
32.768 kHz internal free running oscillator (FRO) with +/- 2% accuracy over the entire voltage and -40 C to 105 C
1 MHz internal low-power oscillator
Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz
Crystal oscillator with 32.768 kHz operating frequency
PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the need for a high-frequency external clock
Clock output function with divider to monitor internal clocks
Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal

Power-Saving Modes

Integrated Power Management Unit (PMU) to minimize power consumption
Reduced power modes: Sleep, deep sleep with RAM retention, power down with RAM and CPU retention, and deep power down with RAM retention
Configurable wake-up options from peripheral interrupts
The micro-tick timer running from the watchdog oscillator, and the real-time clock (RTC) running from the 32.678 kHz clock, can be used to wake the device up from sleep and deep-sleep modes
Power-on reset (POR)
Brown-out-detectors (BOD) with separate thresholds for interrupt and forced reset

Additional Information

Operating from an internal DC-DC converter
Single power supply 1.8 V to 3.6 V
JTAG boundary scan supported
Operating temperature range -40 °C to +105 °C
Available in HTQFP64 and HVQFN48 packages

Part numbers include: LPC5502JBD64, LPC5502JHI48, LPC5504JBD64, LPC5504JHI48, LPC5506JBD64, LPC5506JHI48, LPC55S04JBD64, LPC55S04JHI48, LPC55S06JBD64, LPC55S06JHI48.

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Documentation

Quick reference to our documentation types.

1-5 of 25 documents

^{Data Sheet}
LPC55S3x: Data sheet
PDFRev 3.2Oct 2, 20233.3 MBLPC55S3xEnglish
Supported Parts
^{Data Sheet}
LPC55S0x/LPC550x Data Sheet
PDFRev 1.4Apr 17, 20232.6 MBLPC55S0x_LPC550xEnglish
Supported Parts
^{Application Note}
LPC55Sxx Debug Authentication

PDFRev 3Dec 13, 2023892.7 KBAN13037English, 中文Associated File: AN13037SW
^{Application Note}
Asymmetric Cryptographic Accelerator CASPER

HTML | PDFRev 5Sep 20, 2023645.7 KBAN12445English, 中文Associated File: AN12445SW
^{Application Note}
How to Develop LVGL GUI Demo on Memory-constrained MCU with GUI Guider

PDFRev 0Sep 9, 20222.0 MBAN13730English, 中文Associated File: AN13730SW
^{Application Note}
SRAM3 Usage in LPC55(s)06

PDFRev 0Jun 9, 2022299.9 KBAN13628English
^{Application Note}
How to Use CAN-FD to Transfer Data on LPC5500 Series

PDFRev 3Jun 17, 2021715.6 KBAN12728English, 中文Associated File: AN12728SW
^{Application Note}
AN1902: Assembly Guidelines for QFN and SON Packages Application Note

PDFRev 9.0Mar 30, 20219.3 MBAN1902English
^{Application Note}
Understanding Cap Bank in LPC55(S)xx

PDFRev 0Nov 16, 20201.8 MBAN13057EnglishAssociated File: AN13057SW
^{Application Note}
Using the Code Watchdog Timer

PDFRev 1Nov 6, 20201.0 MBAN12912English
^{Application Note}
LPC55(S)xx Dual-DMA Usage

PDFRev 2Oct 30, 202012.8 MBAN12351English, 中文Associated File: AN12351SW
^{Application Note}
AN12327 - Firmware Update Using Secondary Bootloader

PDFRev 3Oct 30, 20201.5 MBAN12327English, 中文Associated File: AN12327SW
^{Application Note}
LPC55(S)0x CoreMark Porting Guide

PDFRev 0Oct 30, 20207.2 MBAN13035EnglishAssociated File: AN13035SW
^{Application Note}
Hardware Design Guidelines for LPC55(S)xx Microcontrollers

PDFRev 0Oct 30, 20201.1 MBAN13033English, 中文
^{Application Note}
HDMI-CEC Implementation on LPC55xx

PDFRev 1Oct 30, 2020699.0 KBAN12732English, 中文Associated File: AN12732SW
^{Application Note}
Introduction to Boundary Scan of LPC5500

PDFRev 0Oct 30, 20201.7 MBAN13036English
^{Application Note}
NT-Shell Solution on NXP LPC55(S)0x Series

PDFRev 0Oct 30, 20207.7 MBAN13034English
^{Application Note}
LPC55S69 Security Solutions for IoT

PDFRev 1May 15, 2020824.0 KBAN12278English, 中文
^{User Guide}
LPC55S0x/LPC550x User Manual

PDFRev 1.5Dec 21, 202315.7 MBUM11424English
^{Application Note Software}
Application note software for AN12732

ZIPRev 0Dec 19, 20227.3 MBAN12732SWEnglish
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^{Application Note Software}
Application note software for AN13730

ZIPRev 0Sep 9, 202225.9 MBAN13730SWEnglish
^{Application Note Software}
Application note software for AN13057

ZIPRev 0Nov 16, 2020474.4 KBAN13057SWEnglish
^{Application Note Software}
Software package for AN13035

ZIPRev 0Oct 30, 202017.0 MBAN13035SWEnglish
^Errata
LPC55S0x/LPC550x Errata

PDFRev 1.7Dec 19, 2023124.8 KBLPC55S0x_LPC550x_ESEnglish
^{Fact Sheet}
LPC550x MCU Family – Fact Sheet

PDFRev 0Oct 15, 2020364.4 KBLPC550X_S0XMCUFSEnglish
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Design Resources

Design Files

Quick reference to our design files types.

3 design files

Receive the full breakdown. See the product footprint and more in the eCad file.

^Models
Symbol and Footprints for LPC55S0x_LPC550x

ZIPRev 1.0Dec 15, 2020 07:57:00653.4 KBLPC55S0x_BXLs_2020-10-14
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^Models
BSDL Files for LPC55S0x/0x

ZIPRev 1.1Jul 1, 2021 07:57:0013.8 KBLPC55S0x_LPC550x_BSDL_v1
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^Models
IBIS Files for LPC55S0x_LPC550x

ZIPRev 1.1Jun 3, 2021 07:57:004.2 MBLPC55S0x_LPC550x_IBIS_v1
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